1 2-- Copyright (C) 2000-2002 The University of Cincinnati. 3-- All rights reserved. 4 5-- This file is part of VESTs (Vhdl tESTs). 6 7-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE 8-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE 9-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, 10-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY 11-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR 12-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. 13 14-- By using or copying this Software, Licensee agrees to abide by the 15-- intellectual property laws, and all other applicable laws of the U.S., 16-- and the terms of this license. 17 18-- You may modify, distribute, and use the software contained in this 19-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, 20-- June 1991. A copy of this license agreement can be found in the file 21-- "COPYING", distributed with this archive. 22 23-- You should have received a copy of the GNU General Public License 24-- along with VESTs; if not, write to the Free Software Foundation, 25-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 27-- --------------------------------------------------------------------- 28-- 29-- $Id: test135.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ 30-- $Revision: 1.1 $ 31-- 32-- --------------------------------------------------------------------- 33 34PACKAGE electricalSystem IS 35 NATURE electrical IS real ACROSS real THROUGH ground refernce; 36 FUNCTION SIN(X : real) RETURN real; 37 FUNCTION EXP(X : real) RETURN real; 38 FUNCTION SQRT(X : real) RETURN real; 39 FUNCTION POW(X,Y : real) RETURN real; 40END PACKAGE electricalSystem; 41 42USE use.electricalSystem.all; 43ENTITY vpwl IS 44 GENERIC (v0 : real := 0.0); 45 PORT (SIGNAL slope : in real; 46 TERMINAL p, m : electrical); 47END ENTITY vpwl; 48 49ARCHITECTURE one OF vpwl IS 50 QUANTITY v ACROSS i THROUGH p TO m; 51BEGIN 52 v==v0; 53 BREAK WHEN slope'event; 54 v'dot == slope; 55END ARCHITECTURE one; 56 57entity tb is 58end entity; 59architecture atb of tb is 60signal myinput: real; 61 62begin 63 myinput<='1'; 64ARCHITECTURE two OF vpwl IS 65 QUANTITY v ACROSS i THROUGH p TO m; 66 SIGNAL startv : voltage := v0; 67BEGIN 68 BREAK WHEN slope'event; 69 startv <= v WHEN slope'event; 70 v == startv + slope'delayed * startv'last_event; 71END ARCHITECTURE two; 72