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5-- This file is part of VESTs (Vhdl tESTs).
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26
27-- ---------------------------------------------------------------------
28--
29-- $Id: test135.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
30-- $Revision: 1.1 $
31--
32-- ---------------------------------------------------------------------
33
34PACKAGE electricalSystem IS
35    NATURE electrical IS real ACROSS real THROUGH ground refernce;
36    FUNCTION SIN(X : real) RETURN real;
37    FUNCTION EXP(X : real) RETURN real;
38    FUNCTION SQRT(X : real) RETURN real;
39    FUNCTION POW(X,Y : real) RETURN real;
40END PACKAGE electricalSystem;
41
42USE use.electricalSystem.all;
43ENTITY vpwl IS
44    GENERIC (v0 : real := 0.0);
45    PORT (SIGNAL slope : in real;
46          TERMINAL p, m : electrical);
47END ENTITY vpwl;
48
49ARCHITECTURE one OF vpwl IS
50    QUANTITY v  ACROSS i THROUGH p TO m;
51BEGIN
52    v==v0;
53    BREAK WHEN slope'event;
54    v'dot == slope;
55END ARCHITECTURE one;
56
57entity tb is
58end entity;
59architecture atb of tb is
60signal myinput: real;
61
62begin
63	myinput<='1';
64ARCHITECTURE two OF vpwl IS
65    QUANTITY v ACROSS i THROUGH p TO m;
66    SIGNAL startv : voltage := v0;
67BEGIN
68    BREAK WHEN slope'event;
69    startv <= v WHEN slope'event;
70    v == startv + slope'delayed * startv'last_event;
71END ARCHITECTURE two;
72