1 2-- Copyright (C) 2001-2002 The University of Cincinnati. 3-- All rights reserved. 4 5-- This file is part of VESTs (Vhdl tESTs). 6 7-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE 8-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE 9-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, 10-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY 11-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR 12-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. 13 14-- By using or copying this Software, Licensee agrees to abide by the 15-- intellectual property laws, and all other applicable laws of the U.S., 16-- and the terms of this license. 17 18-- You may modify, distribute, and use the software contained in this 19-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, 20-- June 1991. A copy of this license agreement can be found in the file 21-- "COPYING", distributed with this archive. 22 23-- You should have received a copy of the GNU General Public License 24-- along with VESTs; if not, write to the Free Software Foundation, 25-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 27-- --------------------------------------------------------------------- 28-- 29-- $Id: test155.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ 30-- $Revision: 1.1 $ 31-- 32-- --------------------------------------------------------------------- 33 34---------------------------------------------------------------------- 35-- SIERRA REGRESSION TESTING MODEL 36-- Develooped at: 37-- Distriburted Processing Laboratory 38-- University of Cincinnati 39-- Cincinnati 40---------------------------------------------------------------------- 41-- File : test155.ams 42-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) 43-- Created : Sept 2001 44---------------------------------------------------------------------- 45-- Description : 46---------------------------------------------------------------------- 47-- A simple model which has a voltage source. 48-- The output voltage Vout is dependent on the value of VS wrt Vref 49-- If the voltage is above/below Vref, the output is a 0 else output is a 1. 50-- the test is done for checking the correct implementation 51-- of the simple simultaneous if statement with multiple if conditions.it 52-- checks nature declaration, terminal and quantity declarations. 53 54PACKAGE electricalSystem IS 55 NATURE electrical IS real ACROSS real THROUGH ground reference; 56 FUNCTION SIN(X : real) RETURN real; 57 FUNCTION EXP(X : real) RETURN real; 58END PACKAGE electricalSystem; 59use work.electricalSystem.all; 60 61entity test is 62end entity; 63 64architecture atest of test is 65terminal T1,T2:electrical; 66quantity VS across T1; 67quantity Vout: real; 68constant Vref:real:=5.0; 69begin 70 71esource: VS == 5.0; 72 73if (VS<Vref) use 74e1: Vout == 0.0; 75elsif (VS=Vref) use 76e2: Vout == 1.0; 77else 78e3: Vout == 0.0; 79end use; 80 81end architecture atest; 82