1 2-- Copyright (C) 1999-2002 The University of Cincinnati. 3-- All rights reserved. 4 5-- This file is part of VESTs (Vhdl tESTs). 6 7-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE 8-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE 9-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, 10-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY 11-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR 12-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. 13 14-- By using or copying this Software, Licensee agrees to abide by the 15-- intellectual property laws, and all other applicable laws of the U.S., 16-- and the terms of this license. 17 18-- You may modify, distribute, and use the software contained in this 19-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, 20-- June 1991. A copy of this license agreement can be found in the file 21-- "COPYING", distributed with this archive. 22 23-- You should have received a copy of the GNU General Public License 24-- along with VESTs; if not, write to the Free Software Foundation, 25-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 27-- --------------------------------------------------------------------- 28-- 29-- $Id: test169.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ 30-- $Revision: 1.1 $ 31-- 32-- --------------------------------------------------------------------- 33 34----------------------------------------------------------------------------- 35-- Ebers-moll Model for a transistor -- 36-- VHDL-AMS Implementation -- 37-- Developed at the Distributed Processing Lab at the University -- 38-- of Cincinnati -- 39-- by VishwaShanth Kasula on May 10, 1999 -- 40-------------------------------------------------------------------- 41-- Circuit Topology -- 42-- BJT Ebers-Moll static model 43-- Testbench Ckt to evaluate the DC operatioing point of an npn BJT, 44-- Sedra smith page no. 152, fig 4.9 45-------------------------------------------------------------------- 46 47-- Three regions are simulated 48-- Active region, vbb = 4.0 V 49-- Saturation region, vbb = 6.0 V 50-- Cutoff region, vbb = 0.0; 51 52PACKAGE electricalSystem IS 53 NATURE electrical IS real ACROSS real THROUGH ground reference; 54 FUNCTION SIN(X : real) RETURN real; 55 FUNCTION EXP(X : real) RETURN real; 56END PACKAGE electricalSystem; 57 58use work.electricalsystem.all; 59 60entity bjt_npn is 61 generic(isat : real := 1.0e-16; -- Saturation Current 62 bf : real := 100.0; -- Ideal maximus forward current 63 br : real := 1.0; -- ideal maximum reverse current 64 rb : real := 1.0e-5; -- Base resistance 65 rc : real := 1.0e-5; -- collector resistance 66 re : real := 1.0e-5; -- emmiter resistance 67 vaf : real := 100.0); -- Forward Early Voltage 68 port(terminal e,b,c : electrical); 69end bjt_npn; 70 71architecture structure of bjt_npn is 72 terminal b1, c1, e1 : electrical; 73 quantity vbo across ib through b to b1; 74 quantity vco across ic through c to c1; 75 quantity veo across ie through e to e1; 76 quantity vct across Ict through c1 to e1;--current source 77 quantity vbe across ibe through b1 to e1; 78 quantity vbc across ibc through b1 to c1; 79 quantity vce : real := 1.0; -- used to calculate VCE 80 constant gmin : real := 1.0e-12; -- condutsnce in parallel with every pn junction 81 constant vt : real := 0.02589; -- thermal voltage 82 83begin 84 brk : break vbe => 1.0, vbc => -1.0; 85 86 diodecond1 : if(vbe > -5.0*vt) use 87 diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf; 88 elsif (vbe <= -5.0*vt ) use 89 diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf; 90 end use; 91 diodecond2 : if(vbc > -5.0*vt) use 92 diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br; 93 elsif(vbc <= -5.0*vt) use 94 diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br; 95 end use; 96 bres : vbo == ib * 1.0e-6; 97 cres : vco == ic * 1.0e-6; 98 eres : veo == ie * 1.0e-6; 99 kcl_eqn : ie == -1.0*(ib + ic); 100 vcevolt : vce == vbe - vbc; 101 ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf)); 102 103end architecture structure; 104 105 106--***************************************************** 107--TEST BENCH 108use std.textio.all; 109use work.electricalsystem.all; 110 111entity bjt_testbench is 112end bjt_testbench; 113 114architecture structure of bjt_testbench is 115 terminal t1, t2, t3, t4 : electrical ; 116 component bjt_npn_comp 117 generic(isat : real := 1.0e-16; -- Saturation Current 118 bf : real := 100.0; -- Ideal maximus forward current 119 br : real := 1.0; -- ideal maximum reverse current 120 rb : real := 1.0e-5; -- Base resistance 121 rc : real := 1.0e-5; -- collector resistance 122 re : real := 1.0e-5; -- emmiter resistance 123 vaf : real := 100.0); -- Forward Early Voltage 124 port(terminal e,b,c : electrical); 125 end component; 126 for all : bjt_npn_comp use entity work.bjt_npn(structure); 127 128 quantity vcc across icc through t1 to electrical'reference; 129 quantity vrc across irc through t1 to t2; 130 quantity vbb across ibb through t3 to electrical'reference; 131 quantity vre across ire through t4 to electrical'reference; 132 133begin 134 135 bjt : bjt_npn_comp 136 generic map (isat => 1.8104e-15, vaf => 100.0) 137 port map(t4,t3,t2); 138 emres : vre == ire * 3.3e3; 139 ccurr : vcc == 10.0; 140 ecurr : vbb == 6.0; 141 cores : vrc == irc * 4.7e3; 142 143end architecture structure; 144