1 2-- Copyright (C) 2000-2002 The University of Cincinnati. 3-- All rights reserved. 4 5-- This file is part of VESTs (Vhdl tESTs). 6 7-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE 8-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE 9-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, 10-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY 11-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR 12-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. 13 14-- By using or copying this Software, Licensee agrees to abide by the 15-- intellectual property laws, and all other applicable laws of the U.S., 16-- and the terms of this license. 17 18-- You may modify, distribute, and use the software contained in this 19-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, 20-- June 1991. A copy of this license agreement can be found in the file 21-- "COPYING", distributed with this archive. 22 23-- You should have received a copy of the GNU General Public License 24-- along with VESTs; if not, write to the Free Software Foundation, 25-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 27-- --------------------------------------------------------------------- 28-- 29-- $Id: wein_bridge.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ 30-- $Revision: 1.1 $ 31-- 32-- --------------------------------------------------------------------- 33 34--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 35-- REMARKS 36-- ------- 37-- TESTED : Works great for freq of 1.0 KHz - 30.0MHz 38-- COMMENTS : The Values of R1_a and R1_b have to be 18.0k & 32.0K resp. 39-- The freq. is given by the equation 40-- F = 1/(2*PI*R*C) 41-- where R=R3=R4 and 42-- C=C3=C4. 43--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 44--************************************************************************* 45-- Structural Level Model of a WEIN BRIDGE OSCILLATOR. 46-- VHDL-AMS implementation 47-- Developed at Distributed Processing Laboratory 48-- University of Cincinnati 49--************************************************************************* 50 51--######################################################################### 52-- BLOCK DIAGRAM 53-- ------------- 54-- o V_out 55-- | D1 56-- |__________|\_______________ 57-- R1_a R1_b | |/ R2=10.0K | 58-- -----^^^.^^^---o--------/\/\/\/\-----------| 59-- | | T4 |__________/|_______________| 60-- ------- | \| | 61-- -- | D2 | 62-- | |\ | 63-- ------------------|-\ | 64-- | \____________o T3 65-- | / | 66-- -------------------|+/ | 67-- | |/ | 68-- |T1 T2 | 69-- _________o__________||____o_____/\/\/\/\_____| 70-- | | || 71-- | | C4=16.0pF R4=10.0K 72-- | < 73-- C3 |16.0pF < R3=10.0K 74-- ----- < 75-- ----- | 76-- | | 77-- ------- ------- 78-- -- -- 79-- 80--######################################################################### 81 82 PACKAGE electricalsystem IS 83 NATURE electrical IS real ACROSS real THROUGH ground reference; 84 FUNCTION SIN(X:real) RETURN real; 85 FUNCTION COS(X:real) RETURN real; 86 FUNCTION EXP(X:real) RETURN real; 87 END PACKAGE electricalsystem; 88 89------------------------ RESISTOR --------------------------- 90 91use work.electricalsystem.all; 92 93entity resistor is 94 generic(res :real:=1.0 ); 95 port(terminal r_in,r_out: electrical); 96end entity resistor; 97 98architecture behav of resistor is 99 quantity vr across ir through r_in to r_out; 100 101begin 102 vr==ir*res; 103end architecture behav; 104 105------------------------ CAPACITOR--------------------------- 106use work.electricalsystem.all; 107 108entity capacitor is 109 generic(cap :real:=1.0); 110 port(terminal c_in,c_out: electrical); 111end entity capacitor; 112 113architecture behav of capacitor is 114 115quantity vc across ic through c_in to c_out; 116begin 117 init: break vc=>0.0; 118 119 ic==cap*vc'dot; 120end architecture behav; 121 122---------------------------- Diode ----------------------------- 123use work.electricalsystem.all; 124 125entity diode is 126generic ( 127 Isat : real := 1.0e-14; -- saturatioin current 128 n : real := 1.0; -- emmission coefficient 129 bv : real := 1.0; -- reverse breakdown voltage 130 ibv : real := 1.0e-3; -- Breakdown current 131 rds : real := 1.0 -- Ohnic resistamce 132 ); 133port (terminal pos, neg : electrical); 134end diode; 135 136architecture behav of diode is 137 terminal td : electrical; 138 quantity vd across id through td to neg; 139 quantity vrd across ird through pos to td; 140 quantity vdiode : real := 2.0; 141 constant gmin : real := 1.0e-12; -- conductance 142 constant vt : real := 0.026; -- thermal voltage 143begin -- behav 144 brk : break vd => 1.0; 145 diodecondition : if(vd >= -5.0*(vt*n)) use 146 dfow : id == ((isat*(exp(vd/(vt*n)) - 1.0)) + (gmin*vd)); 147 elsif(vd < -5.0*(vt*n) and (vd > -1.0*bv)) use 148 drev: id == ((-1.0*isat) + (gmin*vd)); 149 elsif vd = -1.0*bv use 150 dbv : id == -1.0*ibv; 151 elsif vd < -1.0*bv use 152 blbv : id == -1.0*Isat*(exp(-1.0*((bv + vd)/vt)) - 1.0 + (bv/vt)); 153 end use; 154 diododeres : vrd == ird * rds; 155 diodevolt : vdiode == vd + vrd; 156 157end behav; 158 159-------------------- NPN transistor --------------------------- 160use work.electricalsystem.all; 161 162entity trans_npn is 163 port( terminal emitter,base,collector : electrical); 164end trans_npn; 165 166architecture trans_behav of trans_npn is 167 168terminal t1,t2,t3,t4,t5,e,b :electrical; 169 170constant Lb :real:=0.5e-9; 171constant rb1 :real:=1.0; 172constant rb2 :real:=3.1; 173constant rb3 :real:=2.7; 174constant r_pi :real:=110.0; 175constant c_pi :real:=18.0e-12; 176constant gm :real:=0.88; 177constant cc1 :real:=0.091e-12; 178constant cc2 :real:=0.048e-12; 179constant cc3 :real:=0.023e-12; 180constant Le :real:=0.2e-9; 181constant Rbase:real:=22.0; 182constant Remit:real:=0.6; 183 184 185quantity v1 across i1 through b to t1; 186quantity v2 across i2 through t1 to t2; 187quantity v3 across i3 through t2 to t3; 188quantity v4 across i4 through t3 to t4; 189quantity v_pi across i5 through t4 to t5; 190quantity i6 through t4 to t5; 191quantity v7 across i7 through t1 to collector; 192quantity v8 across i8 through t2 to collector; 193quantity v9 across i9 through t3 to collector; 194quantity v10 across i10 through t5 to e; 195quantity v11 across i11 through collector to t5; 196quantity v_base across i_base through base to b; 197quantity v_emit across i_emit through e to emitter; 198 199 200BEGIN 201 202 v1 ==Lb*i1'dot; 203 v2 ==i2*rb1; 204 v3 ==i3*rb2; 205 v4 ==i4*rb3; 206 v_pi==i5*r_pi; 207 i6 ==c_pi*v_pi'dot; 208 i7 ==cc1*v7'dot; 209 i8 ==cc2*v8'dot; 210 i9 ==cc3*v9'dot; 211 v10 ==Le*i10'dot; 212 i11 ==gm*v_pi; 213 v_base==rbase*i_base; 214 v_emit==remit*i_emit; 215 216end architecture trans_behav; 217 218 219-------------------- PNP transistor --------------------------- 220use work.electricalsystem.all; 221 222entity trans_pnp is 223 port( terminal emitter,base,collector : electrical); 224end trans_pnp; 225 226architecture trans_behav of trans_pnp is 227 228terminal t1,t2,t3,t4,t5,e,b :electrical; 229 230constant Lb :real:=0.5e-9; 231constant rb1 :real:=1.0; 232constant rb2 :real:=3.1; 233constant rb3 :real:=2.7; 234constant r_pi :real:=110.0; 235constant c_pi :real:=18.0e-12; 236constant gm :real:=0.88; 237constant cc1 :real:=0.091e-12; 238constant cc2 :real:=0.048e-12; 239constant cc3 :real:=0.023e-12; 240constant Le :real:=0.2e-9; 241constant Rbase:real:=22.0; 242constant Remit:real:=0.6; 243 244 245quantity v1 across i1 through t1 to b; 246quantity v2 across i2 through t2 to t1; 247quantity v3 across i3 through t3 to t2; 248quantity v4 across i4 through t4 to t3; 249quantity v_pi across i5 through t5 to t4; 250quantity i6 through t5 to t4; 251quantity v7 across i7 through collector to t1; 252quantity v8 across i8 through collector to t2; 253quantity v9 across i9 through collector to t3; 254quantity v10 across i10 through e to t5; 255quantity v11 across i11 through t5 to collector; 256quantity v_base across i_base through b to base; 257quantity v_emit across i_emit through emitter to e; 258 259 260BEGIN 261 262 v1 ==Lb*i1'dot; 263 v2 ==i2*rb1; 264 v3 ==i3*rb2; 265 v4 ==i4*rb3; 266 v_pi==i5*r_pi; 267 i6 ==c_pi*v_pi'dot; 268 i7 ==cc1*v7'dot; 269 i8 ==cc2*v8'dot; 270 i9 ==cc3*v9'dot; 271 v10 ==Le*i10'dot; 272 i11 ==gm*v_pi; 273 v_base==rbase*i_base; 274 v_emit==remit*i_emit; 275 276end architecture trans_behav; 277 278 279--> Constant Voltage source 280--------------------------- 281use work.electricalsystem.all; 282ENTITY voltSource IS 283 generic(amp:real:=22.0); 284 PORT( TERMINAL ta2,tb2 : electrical); 285END voltSource; 286 287ARCHITECTURE voltbehavior OF voltSource IS 288 289terminal t1: electrical; 290quantity V_volt across i_volt through t1 to tb2; 291quantity V_drop across i_drop through ta2 to t1; 292 293BEGIN 294 V_volt == amp; 295 V_drop == i_drop*100.0; 296 297END ARCHITECTURE voltbehavior; 298 299-- ********* Structural Model Of a simple High Frequency OpAmp *********-- 300 301use work.electricalsystem.all; 302entity op_amp is 303port(terminal inverting_ip,non_inverting_ip,output :electrical); 304end entity op_amp; 305 306architecture struct of op_amp is 307 308--> components 309 310COMPONENT trans_pnp is 311 port( terminal emitter,base,collector : electrical); 312end component; 313for all : trans_pnp use entity work.trans_pnp(trans_behav); 314 315COMPONENT trans_npn is 316 port( terminal emitter,base,collector : electrical); 317end component; 318for all : trans_npn use entity work.trans_npn(trans_behav); 319 320component resistor is 321generic(res :real:=1.0 ); 322port(terminal r_in,r_out: electrical); 323end component; 324for all: resistor use entity work.resistor(behav); 325 326component voltsource is 327generic(amp:real:=22.0); 328PORT( TERMINAL ta2,tb2 : electrical); 329end component; 330for all: voltsource use entity work.voltsource(voltbehavior); 331 332terminal t1,t2,t3,t4,t5,t6,t7,t8,t9,t10:electrical; 333terminal V_pos,V_neg: electrical; 334 335BEGIN 336 337 Q01_npn: trans_npn port map(emitter=>T2 ,base=>T1 ,collector=>T9); 338 Q02_npn: trans_npn port map(emitter=>T2 ,base=>T3 ,collector=>T4); 339 Q03_npn: trans_npn port map(emitter=>T5 ,base=>T6 ,collector=>T2); 340 Q04_npn: trans_pnp port map(emitter=>T7 ,base=>T4 ,collector=>T8); 341 Q05_npn: trans_npn port map(emitter=>output,base=>T8 ,collector=>V_pos); 342 343 Res_i1 : resistor generic map(1.0e3) 344 port map(inverting_ip,T1); 345 Res_i2 : resistor generic map(1.0e3) 346 port map(non_inverting_ip,T3); 347 Res_a : resistor generic map(220.0e3) 348 port map(T6,V_pos); 349 Res_c1 : resistor generic map(13.0e3) 350 port map(T9,V_pos); 351 Res_c2 : resistor generic map(13.0e3) 352 port map(V_pos,T4); 353 Res_e4 : resistor generic map(10.0e3) 354 port map(V_pos,T7); 355 Res_b : resistor generic map(20.0e3) 356 port map(T6,V_neg); 357 Res_e3 : resistor generic map(1.3e3) 358 port map(T5,V_neg); 359 Res_c4 : resistor generic map(21.0e3) 360 port map(T8,V_neg); 361 Res_e5 : resistor generic map(12.0e3) 362 port map(output,V_neg); 363 364 vpos : voltsource generic map(amp=>15.0) -- test case 365 port map(V_pos,ground); 366 vneg : voltsource generic map(amp=>-15.0) -- test case 367 port map(V_neg,ground); 368 369end architecture struct; 370 371--------------------------------------------------------------------- 372------------------- WEIN BRIDGE OSCILLATOR --------------------- 373--------------------------------------------------------------------- 374use work.electricalsystem.all; 375 376entity wein_bridge_osc is 377port( terminal signal_out :electrical); 378end entity wein_bridge_osc; 379 380architecture struct of wein_bridge_osc is 381 382--> components 383component op_amp is 384port(terminal inverting_ip,non_inverting_ip,output :electrical); 385end component; 386for all:op_amp use entity work.op_amp(struct); 387 388component diode 389generic ( 390 Isat : real := 1.0e-14; -- saturatioin current 391 n : real := 1.0; -- emmission coefficient 392 bv : real := 1.0; -- reverse breakdown voltage 393 ibv : real := 1.0e-3; -- Breakdown current 394 rds : real := 1.0 -- Ohnic resistamce 395 ); 396port (terminal pos, neg : electrical); 397end component; 398for all : diode use entity work.Diode(behav); 399 400component capacitor is 401generic(cap :real:=1.0); 402port(terminal c_in,c_out: electrical); 403end component; 404for all: capacitor use entity work.capacitor(behav); 405 406component resistor is 407generic(res :real:=1.0 ); 408port(terminal r_in,r_out: electrical); 409end component; 410for all: resistor use entity work.resistor(behav); 411 412terminal t1,t2,t3,t4: electrical; 413 414begin 415 416op_amplifier : op_amp port map(inverting_ip=>t4,non_inverting_ip=>t1,output=>t3); 417 418D1 : diode port map(t3,signal_out); 419D2 : diode port map(signal_out,t3); 420 421R1_a : resistor generic map(18.0e3) 422 port map(t4, ground); 423R1_b : resistor generic map(32.0e3) 424 port map(t4,signal_out); 425R2 : resistor generic map(10.0e3) 426 port map(signal_out,t3); 427R3 : resistor generic map(10.0e3) 428 port map(t1,ground); 429R4 : resistor generic map(10.0e3) 430 port map(t2,t3); 431 432C3 : capacitor generic map(16.0e-12) 433 port map(T1,ground); 434C4 : capacitor generic map(16.0e-12) 435 port map(T1,T2); 436end struct; 437 438---------------------------- Test Bench ----------------------------- 439 440use work.electricalsystem.all; 441 442entity testbench is 443end entity; 444 445architecture basic of testbench is 446 447-->components 448component wein_bridge_osc is 449port( terminal signal_out :electrical); 450end component; 451for all: wein_bridge_osc use entity work.wein_bridge_osc(struct); 452 453terminal t1: electrical; 454 455quantity V_out across i_out through t1 to ground; 456 457BEGIN 458 459osc: wein_bridge_osc port map(T1); 460 461V_out == i_out*1.0e6; 462 463end basic; 464