1 2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20-- code from book 21 22library ieee_proposed; use ieee_proposed.electrical_systems.all; 23 24entity adc_with_ref is 25 port ( quantity v_in : in voltage; 26 signal d_out : out bit; 27 quantity v_ref : in voltage := 1.0 ); 28end entity adc_with_ref; 29 30-- end code from book 31 32 33architecture signal_flow of adc_with_ref is 34begin 35end architecture signal_flow; 36 37 38 39library ieee_proposed; use ieee_proposed.electrical_systems.all; 40 41entity inline_17a is 42 43end entity inline_17a; 44 45 46architecture test of inline_17a is 47 48begin 49 50 block_1 : block is 51 52 quantity sensor_in : voltage; 53 signal sensor_data_out : bit; 54 55 begin 56 57 sensor_in == 5.0; 58 59 -- code from book 60 61 default_adc : entity work.adc_with_ref(signal_flow) 62 port map ( sensor_in, sensor_data_out ); 63 64 -- end code from book 65 66 end block block_1; 67 68 69 block_2 : block is 70 71 quantity sensor_in : voltage; 72 signal sensor_data_out : bit; 73 constant v_supply : voltage := 10.0; 74 75 begin 76 77 sensor_in == 5.0; 78 79 -- code from book 80 81 fixed_adc : entity work.adc_with_ref(signal_flow) 82 port map ( sensor_in, sensor_data_out, v_ref => v_supply / 2.0 ); 83 84 -- end code from book 85 86 end block block_2; 87 88end architecture test; 89