1 2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20entity bottom is 21 port ( -- . . . ); 22 -- 23 port_name : in bit := '0' ); 24 -- 25end entity bottom; 26 27-------------------------------------------------- 28 29architecture bottom_arch of bottom is 30 31 signal bot_sig : -- . . .; -- 5 32 -- 33 bit; 34 -- 35 36 procedure proc ( -- . . . ) is 37 -- 38 param_name : in bit := '0' ) is 39 -- 40 variable v : -- . . .; -- 6 41 -- 42 bit; 43 -- 44 begin 45 -- . . . 46 -- 47 report "--6: " & v'path_name; 48 report "--6: " & v'instance_name; 49 -- 50 end procedure proc; 51 52begin 53 54 delays : block is 55 constant d : integer := 1; -- 7 56 begin 57 -- . . . 58 -- 59 assert false report "--7: " & d'path_name; 60 assert false report "--7: " & d'instance_name; 61 -- 62 end block delays; 63 64 func : block is 65 begin 66 67 process is 68 variable v : -- . . .; -- 8 69 -- 70 bit; 71 -- 72 begin 73 -- . . . 74 -- 75 report "--5: " & bot_sig'path_name; 76 report "--5: " & bot_sig'instance_name; 77 report "--8: " & v'path_name; 78 report "--8: " & v'instance_name; 79 proc(param_name => open); 80 wait; 81 -- 82 -- 83 end process; 84 85 end block func; 86 87end architecture bottom_arch; 88