1 2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20package inline_03_defs is 21 22 -- code from book: 23 24 attribute cell_name : string; 25 attribute pin_number : positive; 26 attribute max_wire_delay : delay_length; 27 attribute encoding : bit_vector; 28 29 30 type length is range 0 to integer'high 31 units nm; 32 um = 1000 nm; 33 mm = 1000 um; 34 mil = 25400 nm; 35 end units length; 36 37 type coordinate is record 38 x, y : length; 39 end record coordinate; 40 41 attribute cell_position : coordinate; 42 43 -- end of code from book 44 45end package inline_03_defs; 46 47 48 49 50entity inline_03 is 51 52end entity inline_03; 53 54 55---------------------------------------------------------------- 56 57 58architecture std_cell of inline_03 is 59 60 use work.inline_03_defs.all; 61 62 signal enable, clk : bit; 63 64 type state_type is (idle_state, other_state); 65 66 -- code from book: 67 68 attribute cell_name of std_cell : architecture is "DFF_SR_QQNN"; 69 attribute pin_number of enable : signal is 14; 70 attribute max_wire_delay of clk : signal is 50 ps; 71 attribute encoding of idle_state : literal is b"0000"; 72 attribute cell_position of the_fpu : label is ( 540 um, 1200 um ); 73 74 -- end of code from book 75 76begin 77 78 the_fpu : block is 79 begin 80 end block the_fpu; 81 82 process is 83 use std.textio.all; 84 variable L : line; 85 begin 86 write(L, std_cell'cell_name); 87 writeline(output, L); 88 write(L, enable'pin_number); 89 writeline(output, L); 90 write(L, clk'max_wire_delay); 91 writeline(output, L); 92 write(L, idle_state[return state_type]'encoding); 93 writeline(output, L); 94 write(L, length'image(the_fpu'cell_position.x)); 95 write(L, ' '); 96 write(L, length'image(the_fpu'cell_position.y)); 97 writeline(output, L); 98 99 wait; 100 end process; 101 102end architecture std_cell; 103