1
2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20entity inline_15 is
21
22end entity inline_15;
23
24
25----------------------------------------------------------------
26
27
28architecture test of inline_15 is
29begin
30
31
32  process_3_c : process is
33
34    -- code from book:
35
36    subtype name is string(1 to 20);
37    type display_string is array (integer range 0 to 19) of character;
38
39    variable item_name : name;
40    variable display : display_string;
41
42    --
43
44    subtype big_endian_upper_halfword is bit_vector(0 to 15);
45    subtype little_endian_upper_halfword is bit_vector(31 downto 16);
46
47    variable big : big_endian_upper_halfword;
48    variable little : little_endian_upper_halfword;
49
50    -- end of code from book
51
52  begin
53
54    -- error: Incompatible types for assignment
55    -- display := item_name;  -- ilegal
56
57    item_name := (others => 'A');
58
59    little := x"AAAA";
60
61    -- code from book:
62
63    display := display_string(item_name);
64
65    --
66
67    big := little;
68    little := big;
69
70    -- end of code from book
71
72    wait;
73  end process process_3_c;
74
75
76  ----------------
77
78
79end architecture test;
80