1
2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20entity inline_14 is
21
22end entity inline_14;
23
24
25----------------------------------------------------------------
26
27
28architecture test of inline_14 is
29
30  signal PC, functional_next_PC, equivalent_next_PC : integer := 0;
31
32begin
33
34
35  block_3_p : block is
36    port ( next_PC : out integer );
37    port map ( next_PC => functional_next_PC );
38  begin
39
40    -- code from book:
41
42    PC_incr : next_PC <= PC + 4 after 5 ns;
43
44    -- end of code from book
45
46  end block block_3_p;
47
48
49  ----------------
50
51
52  block_3_q : block is
53    port ( next_PC : out integer );
54    port map ( next_PC => equivalent_next_PC );
55  begin
56
57    -- code from book:
58
59    PC_incr : process is
60    begin
61      next_PC <= PC + 4 after 5 ns;
62      wait on PC;
63    end process PC_incr;
64
65    -- end of code from book
66
67  end block block_3_q;
68
69
70  ----------------
71
72
73  stimulus : process is
74  begin
75    for i in 1 to 10 loop
76      PC <= i after 20 ns;
77      wait for 20 ns;
78    end loop;
79    wait;
80  end process stimulus;
81
82  verifier :
83  assert functional_next_PC = equivalent_next_PC
84    report "Functional and equivalent models give different results";
85
86
87end architecture test;
88