1
2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20library ieee;  use ieee.math_real.all;
21library ieee_proposed;  use ieee_proposed.electrical_systems.all;
22
23entity opamp_2pole_res is
24  generic ( A : real := 1.0e6;	    -- open loop gain
25            rin : real := 1.0e6;    -- input resistance
26            rout : real := 100.0;   -- output resistance
27            fp1 : real := 5.0;	    -- first pole
28            fp2 : real := 9.0e5 );  -- second pole
29  port ( terminal in_pos, in_neg, output : electrical );
30end entity opamp_2pole_res;
31
32----------------------------------------------------------------
33
34architecture ltf of opamp_2pole_res is
35
36  constant wp1 : real := fp1 * math_2_pi;
37  constant wp2 : real := fp2 * math_2_pi;
38  constant num : real_vector := (0 => wp1 * wp2 * A);
39  constant den : real_vector := (wp1 * wp2, wp1 + wp2, 1.0);
40  quantity v_in across i_in through in_pos to in_neg;
41  quantity v_out across i_out through output;
42
43begin
44
45  i_in  == v_in / rin;  -- input current
46
47  v_out == v_in'ltf(num, den) + i_out * rout;
48
49end architecture ltf;
50