1GPLCVER_2.12a of 05/16/07 (Linux-elf). 2Copyright (c) 1991-2007 Pragmatic C Software Corp. 3 All Rights reserved. Licensed under the GNU General Public License (GPL). 4 See the 'COPYING' file for details. NO WARRANTY provided. 5Today is Wed May 30 09:17:41 2007. 6 ** GPL CVER VERILOG SIMULATOR HELP MESSAGE ** 7 8 GPL Cver is a Verilog HDL simulator following the 1995 IEEE P1364 standard 9 with some 2001 P1364 LRM features added and some modifications to match 10 actual behavior of de facto standard XL simulator. Modeling in C/C++ and 11 Verilog using PLI 1 and PLI 2 interfaces is supported. PLI implementation 12 follows 2001 P1364 LRM. See release notes in doc directory for list of 13 P1364 2001 supported features and list of known problems. 14 15 Usage: cver [intermixed options and Verilog source files]. 16 17 Command line and -f command file options must be in lower case and must 18 begin with a - or +. Each option requires a separate - or +. Type 19 'cver -?' or 'cver -h' to generate this help message. To enter the 20 Verilog statement interactive debugger (press interrupt (^c) or execute 21 $stop), then type :help' for interactive debugger help. 22 23 It is assumed that you already know Verilog and have access to a P1364 LRM 24 or other Verilog documentation. Cver supports both PLI (Programming 25 Language Interface) 1 tf_ and acc_ and PLI 2 vpi_ utility, design object 26 and callback routines using +loadpli1= and +loadvpi= dynamic PLI load 27 options defined below. Both old PLI 1 and new PLI 2 libraries can be 28 dynamically loaded during one run. See examples in examples.vpi, 29 examples.tf and examples.acc release directories for examples showing how 30 to link and run PLI models. Cver contains a number of new system tasks 31 and functions. See systasks.1 man page in the doc directory for 32 definition of every system task and system function supported by Cver. 33 34 Cver generally produces results matching other simulators even when other 35 simulators differ from P1364 standard up to differences in event order. 36 However, Cver does not change port direction because of net connection 37 direction (i.e. treat nets with wrong side of port drivers as inouts) 38 unless the +change_port_type option is selected. It is suggested that 39 you change your designs so port type changing is not needed, but for full 40 compatibility with other simulators always run with +change_port_type 41 option. Cver implements pulse (glitch) detection for gates as well as 42 paths. This may cause some simulation result differences. This more 43 stringent pulse analysis is consistent with Cver's intended use as 44 accurate gate level simulator. 45 46 Since all options are collected before processing, if any options are 47 duplicated, the rightmost (last) will be used. All Cver options are 48 listed in this help message. Any other option will be ignored by Cver 49 although it may be scanned and used by a user PLI routine. All options 50 not listed in this help message will have warning 506 emitted for minus 51 options and inform 410 for plus options. 52 53 Options defined in the IEEE P1364 reference manual are supported and have 54 the following effect: 55 56 -f [file] Read options and source file names from [file] until it is 57 exhausted at which point continue reading from command line. May 58 be nested. 59 -l [file] By default all output is written to stdout and to log file 60 verilog.log. -l changes to log file [file]. System task 61 $log([file]) changes to log file [file] during simulation, $nolog 62 turns off log file output. Added system task $flushlog calls OS 63 fflush on log file. $reset does not reset log file. 64 -s Stop just before starting simulation and enter interactive debugger. 65 -i [file] Read interactive debugger commands from file [file] the first 66 time interactive mode is entered (usually with -s but possibly by 67 $stop or interrupt signal (^c)). Nested -i [file] options are 68 chained not nested. 69 -c Translate source and all referenced library models only. Ends just 70 before loading the translated model into memory. 71 -w Suppress all warning messages. See +suppress_warns added option for 72 suppression of warnings and informs by message number. 73 -d Dump source that is constructed from internal representation. All 74 parameters are replaced by their constant value in the 75 reconstructed source output. Debugger source listing lists lines 76 from source files instead of reconstructing source. 77 -q Quiet mode. Do not print normal progress messages. Opposite 78 of -q is +verbose that prints even more progress messages than normal. 79 +mindelays, +typdelays, +maxdelays Choose either minimum, typical or 80 maximum value from any constant (min:typ:max) forms in source. 81 Selection is made during input scanning so min:typ:max forms 82 become constant numbers at translation time. 83 -t Trace procedural statement execution. Use -et to trace event 84 processing. In other simulators, -t means both -t and -et. 85 $settrace, $setevtrace, $cleartrace, $clearevtrace to control 86 tracing during simulation. 87 +libnocell Ignore `celldefine directives in source and libraries. This 88 should not be used if delay back annotation is used since it will 89 probably cause annotation to fail. 90 +notimingchecks After checking for correct syntax, ignore timing checks. 91 -u Ignored. For all upper case, use an OS filter command to convert 92 source to all upper case. 93 94 Only default and +librescan library scanning order supported. By default 95 all library files from -v [file] and all directories of library elements 96 from -y [directory] are scanned from first to last according to input option 97 order. If unresolved names remain after completion of a pass, the list is 98 rescanned from the beginning. If +librescan option is selected, unresolved 99 names are resolved one at a time in order they are first seen. After a 100 name has been resolved, the next name in order is resolved by rescanning 101 from the beginning of library list. Options to control order dependent 102 resolution and +libnamehide are not implemented. Library options are: 103 104 Cver also now supports configuration files for selecting libraries and 105 design components following the Verilog 2005 LRM description. See LRM 106 section 13. 107 108 +config [config file name] Use this option to specify library file 109 mapping using new 2001 config feature. See LRM section 13 and 110 see the tests_and_exmaples/v2001/config directory for examples. 111 -v [file] Treat [file] as a library containing module and UDP 112 definitions. File is sequentially searched for definitions that 113 resolve unresolved names. Within a -v file, if a name if defined 114 before use, it is resolved before moving to next library element. 115 -y [directory] Treat every file in [directory] as a -v library although 116 usually each file will only contain one definition. File name in 117 directory along with +libext+ option used to find unresolved name. 118 +libext+ In -y directory files, name resolution uses file names. If 119 no +libext+ option is present only files whose name exactly 120 matches an unresolved module or primitive will be read. There can 121 be no extension. Normally, each -y file will contain the 122 definition for exactly one element but if more elements are present 123 they will be used to resolve other unresolved elements. Use 124 +libext+[extension with dot]+[extension with dot]+... to cause 125 file name extensions to be removed before matching file names to 126 unresolved element names. Only one +libext+ option may appear and 127 matching is in order when library extensions do not follow the 128 simple .[suffix name] convention. If all files in -y directories 129 end with either .v or .V (a common case), use +libext+.v+.V+ 130 +librescan Rescan to beginning of library file and directory list after 131 every unresolved name is resolved. At most one name resolved per 132 library pass. 133 +libverbose Emit detailed trace messages giving resolution order and 134 reason a particular element was resolved at the particular place. 135 136 +show_canceled_e Path and gate (1 bit continuous assignments implemented 137 as gates) outputs set to X when pulses occur that cause scheduled 138 but not matured events to be canceled because second input edge 139 occurs before output has changed (switched). The output 140 remains at X until another input edge causes an output change 141 because it is unknown if a pulse (glitch) will cause output 142 switching. Some other simulators use a less pessimistic algorithm 143 that assumes pulses never cause switching and schedule a change 144 from X back to original output value on trailing edge of pulse. If 145 your model will not run, use the +warn_canceled_e instead of this 146 option and examine warnings. Cver does not allow only some 147 paths and gates to use pulse X showing using specify section 148 directives because X showing does not slow down simulation. 149 Normally X from a pulse is shown on leading edge of glitch. Use 150 +pulse_e_style_ondetect to cause X to be shown(driven) when pulse 151 detected from input change. Option is standardized replacement for 152 previous +spikes option. 153 +noshow_canceled_e Path and gate outputs not driven (shown) as X when 154 pulses occur (second input change earlier than selected delay). 155 This is the default (normally it is not needed). It selects normal 156 Verilog inertial delay algorithm where the latest input change 157 causes the previously scheduled but unmatured event to be canceled. 158 +pulse_e_style_ondetect If +show_canceled_e option selected, this option 159 causes output to be set to X (shown) when the pulse (glitch) is 160 detected. If this option is not selected, output is set to X 161 (shown) when the pulse propagates to an output. This option 162 selects a more pessimistic (starting earlier) X region. 163 +pulse_e_style_onevent If +show_canceled_e option selected, this option 164 selects the default output setting to X (showing) option that sets 165 output to X when glitch propagates to output (leading edge is time 166 at which the event scheduled latest matures). There is no reason 167 to use this option since it is default. Control of X showing for 168 individual gates and paths is not supported. 169 +warn_canceled_e Emit warning for every gate (including UDP) or path event 170 cancel (inertial cancel and reschedule). This option may cause 171 voluminous output so the $suppress_warns and $allow_warns system 172 tasks can be used to select particular time periods when warnings 173 are emitted. This option and +show_canceled_e are unrelated so both 174 error messages and x showing (injection) may be enabled. 175 +nowarn_canceled_e Because this option is the default it is never needed 176 Last of all +warn_canceled_e and +nowarn_canceled_e is used. 177 178 The following two options for dynamically loading user PLI libraries are 179 not explicitly defined in IEEE P1364 reference manual but are supported 180 by all modern simulators: 181 182 +loadpli1=[.so library]:[boostrap routines] Load [.so library] dynamic 183 library containing user PLI 1 model and execute each bootstrap 184 routine. [bootstrap routines] is a comma separated list of C 185 routines. List may be empty but : is still required. No spaces 186 are allowed around the equal sign, the colon or commas separating 187 bootstrap C routine names. All dynamic libraries defined by 188 +loadpli1= options are first loaded using OS dlopen mechanism and 189 then all bootstrap routines are executed before elaboration begins. 190 The OS specific dynamic library suffix (.so on Linux) may be 191 omitted. If omitted and the [.so library] is not found in any 192 LD_LIBRARY_PATH directory, the dynamic library suffix is added and 193 the LD_LIBRARY_PATH directories are searched again. 194 195 Each [bootstrap routines] list routine must return a pointer to a 196 s_tfcell veriusertfs table that ends with zero value type field. 197 Multiple +loadpli1= options are allowed and just before elaboration 198 all [bootstrap routines] for every +loadpli1= option are executed. 199 Each s_tfcell returned table is added to one design wide master 200 s_tfcell table in option and routine in list order. The master 201 table defines all PLI 1 system functions and tasks used during a 202 simulation run. The [bootstrap routines] must not call any PLI 203 routines. Any C file containing [bootstrap routines] list must 204 include both veriuser.h and cv_veriuser.h files. Some OS shells 205 may require quoting and escaping option separators and file names 206 within the +loadpli1= option string. Problem can be avoided by 207 coding +loadpli1= option in a -f command argument file. See release 208 examples.tf directory in tests_and_examples directory for example 209 PLI 1 programs and make files specific to your operating system. 210 +loadvpi=[.so library]:[boostrap routines] Load [.so library] dynamic 211 library containing user PLI 2 vpi model and execute each bootstrap 212 routine. [bootstrap routines] is a comma separated list of C/C++ 213 routines. List may be empty but : is still required. No spaces 214 are allowed around the equal sign, the colon or commas separating 215 bootstrap C routine names. All dynamic libraries defined by 216 +loadvpi= options are first loaded using OS dlopen mechanism and 217 then all bootstrap routines are executed before elaboration begins. 218 The OS specific dynamic library suffix (.so on Linux) may be 219 omitted. If omitted and the [.so library] is not found in any 220 LD_LIBRARY_PATH directory, the dynamic library suffix is added and 221 the LD_LIBRARY_PATH directories are searched again. 222 223 Each [bootstrap routines] is saved on an ordered list and executed 224 in order before elaboration begins. Normally [bootstrap routines] 225 will execute routines in vlog_startup_routines table, but any PLI 2 226 vpi routines callable before elaboration may be called including 227 vpi_register_systf and vpi_register_cb PLI 2 routines. Some OS 228 shells may require quoting and escaping option separators and file 229 names within the +loadvpi= option string. Problem can be avoided by 230 coding +loadvpi= option in a -f command argument file. See release 231 examples.vpi directory for example PLI 1 programs and make files 232 specific to your operating system. 233 234 The following other options not defined in the IEEE P1364 reference manual 235 are supported: 236 +verbose Print various simulation progress messages and design component 237 counts. Memory sizes do not count memory used by udp tables. 238 +maxerrors [number] Normally translation terminates after 32 239 errors. Use this option to change the number. 0 means no limit. 240 Option applies to translation only, simulation is never stopped. 241 -e Turn off printing of non fatal error messages. 242 -informs Turn on printing of informatory messages. Off by default. 243 Informs may be emitted during translation and during simulation. 244 Enable this option to determine if a plus option is misspelled and 245 to cause OS error message description strings to be printed. 246 Option will probably produce voluminous output unless 247 +suppress_warns+[+ separated list] option(s) also used. 248 -et Turn on event tracing. Option is similar to the -t (or $settrace) 249 option but -t only traces procedural execution. To dynamically 250 control event tracing use $setevtrace and $clearevtrace system 251 tasks. Option produces voluminous output. Use -t and -et to 252 duplicate other simulator -t tracing. 253 +tracefile [name] Set the output file for any trace output (either 254 statement or event). Use $settracefile system task to change 255 trace file during execution. Name can be stdout and if no option 256 or $tracefile, defaults to stdout and log file. $flushlog system 257 task flushes this file during simulation. 258 +printstats Print tables of design contents. Primitives, instances, 259 and wires that will use silicon area are tabulated. More 260 detailed alternative to $showallinstances. 261 +printallstats Option equivalent to +printstats but additionally prints 262 the declarative content of every module. 263 +suppress_warns+ Individual warning and informatory messages can be 264 suppressed (not errors) by including a + separated list. i.e. 265 +suppress_warns+403+502+507+564+. All such options are combined. 266 The $suppress_warns([comma separated list]) and $allow_warns 267 system tasks can be used during simulation for the same effect. 268 +remove_gate_0delays Change all gates with #0 or #(0, 0, 0) delay to no 269 delay (1 bit continuous assigns implemented as gates). Option can 270 significantly speed up simulation but in very rare situation cause 271 simulation to fail (#0 delays used to mask races). If you see a 272 large simulation speed up from option, you can probably speed up 273 simulation even more by recoding most common cells as udps. Option 274 needed because some simulators only allow delay annotation if gate 275 has a delay coded in source. 276 +nokeepcommands Do not save interactive commands to history list. By 277 default, Interactive commands are saved to history list. The 278 $keepcommands; and $nokeepcommands; system tasks enable and disable 279 saving of of history during simulation. Option should be used when 280 interactive input comes from $input or from shell pipe to stdin. 281 +define+[symbol] or +define+[symbol]=[string] Define back quote macro 282 symbol [symbol] with an empty text string (first form) for use with 283 `ifdef and `ifndef macro facility. [symbol] does not include back 284 quote. Second form defines symbol with value [string]. [String] 285 must not contain white space but can contain anything else including 286 surrounding quotes. Escaped surrounding quotes are converted to 287 normal quotes while non escaped will probably be removed 288 by your shell. The $scan$plusargs system task is an alternative 289 for setting preprocessor values into variables. 290 +incdir+[path]+[path]+...+ Define paths that are searched for `include 291 files when `include file not found in current directory. Only 292 `include files that are non absolute paths (not staring with '/' 293 or '.' or '..' or '~') are searched for using +incdir paths. 294 Paths that do not end with '/' have a '/' path separator appended 295 to end. For file included in different directory, files included 296 from it are still searched for in original (not include file) 297 directory. Multiple +incdir+ options may be specified. Paths 298 directories are searched in order of +incdir+ options. 299 +sdf_log_file [file] File is used for SDF annotation instead of default 300 writing of SDF messages and errors to Verilog log file. 301 +sdf_annotate [file] or +sdf_annotate [file]+[scope reference] File must 302 be in IEEE P1497 standard delay file format. File is read and used 303 to set delay and specify values. +mindelays, +typdelays or 304 +maxdelays setting used to select rtriple value. Multiple 305 +sdf_annotate options (and files) allowed. If +[scope reference] 306 provided, SDF path references relative to scope. Otherwise, SDF 307 paths rooted (context is entire design). Annotation files processed 308 in option order. Alternatively, $sdf_annotate system task can be 309 used to annotate delays. See systsks.1 man page for documentation. 310 Large designs that require large SDF files load somewhat faster if 311 command line option instead of system task is used. 312 +sdfverbose Emit trace messages giving new delay value for every delay 313 changed during +sdf_annotate delay annotation. Option can generate 314 voluminous output. 315 +sdf_noerrors Do not emit SDF annotation error messages. SDF errors do 316 not stop simulation but cause SDF object delay setting to be skipped 317 so +maxerrors error limit does not apply. Use this option to turn 318 off printing of SDF error messages. 319 +sdf_nowarns Do not emit warning messages during SDF annotation. SDF 320 warnings and informs can also be suppressed by message number 321 using +suppress_warns+ option. 322 +switchverbose Emit trace and size messages for inout and tran gate 323 switch channels elaboration. Use this option to print progress 324 messages when simulating models with very large switch channels. 325 +change_port_type Some designs require ports that are not declared as 326 inout but are connected as inouts and require bidirectional signal 327 flow for correct simulation have their port type changes to inout. 328 Use this option to cause port direction to be changed to inout for 329 input ports with loconn drivers and for output ports with highconn 330 drivers. WARNING: Use of this option may be required to match 331 results of other simulators that use port collapsing algorithm. 332 +no_separate_nb_queue Cver non blocking event scheduling algorithm has 333 changed to match XL (all non blocking events scheduled only 334 after all #0 events processed). Use this option for backward 335 compatibility with old cver algorithm that mixed non blocking 336 eventing in the #0 queue. If using this option changes your 337 results, your circuit probably has a race. 338 +nospecify Simulation run with specify section ignored. This option 339 causes specify section to be read and parsed but it is discarded 340 before simulation. +nospecify of course implies +notimingchecks. 341 +nointeractive Option turns off interactive environment, interrupt signal 342 (^c) causes immediate termination. $stop causes a warning to be 343 printed without stopping. Suppress warning 560 to silently ignore 344 stops. 345 +snapshot If +nointeractive option is selected, if interrupt signal 346 (^c) is generated, this option causes a port mortem activity 347 snapshot to be printed before program termination. Debugger 348 :where and $snapshot system task produces same output without 349 ending simulation. 350**Special help mode successfully completed. 351