1-- Structural VAMS generated by gnetlist
2-- Secondary unit
3
4ARCHITECTURE simple_arc OF BJT_transistor_simple IS
5	terminal unnamed_net8 	:  electrical;
6	terminal unnamed_net7 	:  electrical;
7	terminal unnamed_net5 	:  electrical;
8	terminal unnamed_net4 	:  electrical;
9	terminal unnamed_net1 	:  electrical;
10BEGIN
11-- Architecture statement part
12
13  SP1 : ENTITY SP_DIODE(SPICE_Diode_Model)
14	GENERIC MAP (
15			VT => VT,
16			AF => AF,
17			KF => KF,
18			PT => PT,
19			EG => EG,
20			M => ME,
21			PB => PE,
22			TT => TF,
23			CJ0 => CJE,
24			ISS => ISS)
25	PORT MAP (	ANODE => unnamed_net8,
26			KATHODE => unnamed_net5);
27
28  CS2 : ENTITY SPICE_cs(current_controlled)
29	GENERIC MAP (
30			N => BF,
31			VT => VT,
32			ISS => ISS)
33	PORT MAP (	urt => unnamed_net4,
34			lrt => unnamed_net5,
35			ult => unnamed_net1,
36			llt => unnamed_net8);
37
38  CAP2 : ENTITY CAPACITOR
39	PORT MAP (	LT => unnamed_net5,
40			RT => unnamed_net1);
41
42  CAP1 : ENTITY CAPACITOR
43	PORT MAP (	LT => unnamed_net1,
44			RT => unnamed_net4);
45
46  GND1 : ENTITY GROUND_NODE
47	PORT MAP (	T1 => unnamed_net7);
48
49  CAP3 : ENTITY CAPACITOR
50	GENERIC MAP (
51			c => CCS)
52	PORT MAP (	LT => unnamed_net7,
53			RT => unnamed_net4);
54
55  RES_emitter : ENTITY RESISTOR
56	GENERIC MAP (
57			r => RE)
58	PORT MAP (	RT => unnamed_net5,
59			LT => emitter);
60
61  RES_collector : ENTITY RESISTOR
62	GENERIC MAP (
63			r => RC)
64	PORT MAP (	RT => collector,
65			LT => unnamed_net4);
66
67  RES_base : ENTITY RESISTOR
68	GENERIC MAP (
69			r => RB)
70	PORT MAP (	RT => unnamed_net1,
71			LT => base);
72END ARCHITECTURE simple_arc;
73