1* ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER 2 3*** SUBCIRCUIT DEFINITIONS 4.SUBCKT NAND in1 in2 out VDD 5* NODES: INPUT(2), OUTPUT, VCC 6M1 out in2 Vdd Vdd p1 W=3u L=1u 7M2 net.1 in2 0 0 n1 W=3u L=2u 8M3 out in1 Vdd Vdd p1 W=3u L=1u 9M4 out in1 net.1 0 n1 W=3u L=2u 10.ENDS NAND 11 12.SUBCKT ONEBIT 1 2 3 4 5 6 13* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC 14X1 1 2 7 6 NAND 15X2 1 7 8 6 NAND 16X3 2 7 9 6 NAND 17X4 8 9 10 6 NAND 18X5 3 10 11 6 NAND 19X6 3 11 12 6 NAND 20X7 10 11 13 6 NAND 21X8 12 13 4 6 NAND 22X9 11 7 5 6 NAND 23.ENDS ONEBIT 24 25.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 26* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, 27* CARRY-IN, CARRY-OUT, VCC 28X1 1 2 7 5 10 9 ONEBIT 29X2 3 4 10 6 8 9 ONEBIT 30.ENDS TWOBIT 31 32.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 33* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), 34* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC 35X1 1 2 3 4 9 10 13 16 15 TWOBIT 36X2 5 6 7 8 11 12 16 14 15 TWOBIT 37.ENDS FOURBIT 38 39*** DEFINE NOMINAL CIRCUIT 40VCC 99 0 DC 3.3V 41VIN1A 1 0 PULSE(0 3 0 10NS 10NS 10NS 50NS) 42VIN1B 2 0 PULSE(0 3 0 10NS 10NS 20NS 100NS) 43VIN2A 3 0 PULSE(0 3 0 10NS 10NS 40NS 200NS) 44VIN2B 4 0 PULSE(0 3 0 10NS 10NS 80NS 400NS) 45VIN3A 5 0 PULSE(0 3 0 10NS 10NS 160NS 800NS) 46VIN3B 6 0 PULSE(0 3 0 10NS 10NS 320NS 1600NS) 47VIN4A 7 0 PULSE(0 3 0 10NS 10NS 640NS 3200NS) 48VIN4B 8 0 PULSE(0 3 0 10NS 10NS 1280NS 6400NS) 49X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT 50*RBIT0 9 0 100K 51*RBIT1 10 0 100K 52*RBIT2 11 0 100K 53*RBIT3 12 0 100K 54*RCOUT 13 0 100K 55 56.TRAN 1NS 1000NS 57 58.model n1 nmos level=8 version=3.3.0 59.model p1 pmos level=8 version=3.3.0 60 61.END 62