1entity ramb_test is 2end entity; 3 4library ieee; 5use ieee.std_logic_1164.all; 6 7library unisim; 8use unisim.vcomponents.all; 9 10architecture test of ramb_test is 11 signal doa : std_logic_vector(31 downto 0); 12 signal dopa : std_logic_vector(3 downto 0); 13 signal dob : std_logic_vector(31 downto 0); 14 signal dopb : std_logic_vector(3 downto 0); 15 signal addra : std_logic_vector(13 downto 0); 16 signal addrb : std_logic_vector(13 downto 0); 17 signal ena : std_logic := '1'; 18 signal enb : std_logic := '1'; 19 signal wea : std_logic_vector(3 downto 0) := X"0"; 20 signal web : std_logic_vector(3 downto 0) := X"0"; 21 signal clka : std_logic := '0'; 22 signal dia : std_logic_vector(31 downto 0); 23 signal dipa : std_logic_vector(3 downto 0); 24 signal clkb : std_logic := '0'; 25 signal rsta : std_logic := '0'; 26 signal rstb : std_logic := '0'; 27 signal regcea : std_logic := '1'; 28 signal regceb : std_logic := '1'; 29 signal dib : std_logic_vector(31 downto 0); 30 signal dipb : std_logic_vector(3 downto 0); 31begin 32 33 RAMB16BWER_inst : entity work.RAMB16BWER 34 generic map ( 35 -- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36 36 DATA_WIDTH_A => 9, 37 DATA_WIDTH_B => 9, 38 -- DOA_REG/DOB_REG: Optional output register (0 or 1) 39 DOA_REG => 0, 40 DOB_REG => 0, 41 -- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST 42 EN_RSTRAM_A => TRUE, 43 EN_RSTRAM_B => TRUE, 44 -- INITP_00 to INITP_07: Initial memory contents. 45 INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", 46 INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", 47 INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", 48 INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", 49 INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", 50 INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", 51 INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", 52 INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", 53 -- INIT_00 to INIT_3F: Initial memory contents. 54 INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", 55 INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", 56 INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", 57 INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", 58 INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", 59 INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", 60 INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", 61 INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", 62 INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", 63 INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", 64 INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", 65 INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", 66 INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", 67 INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", 68 INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", 69 INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", 70 INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", 71 INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", 72 INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", 73 INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", 74 INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", 75 INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", 76 INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", 77 INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", 78 INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", 79 INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", 80 INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", 81 INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", 82 INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", 83 INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", 84 INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", 85 INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", 86 INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", 87 INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", 88 INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", 89 INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", 90 INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", 91 INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", 92 INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", 93 INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", 94 95 INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", 96 INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", 97 INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", 98 INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", 99 INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", 100 INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", 101 INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", 102 INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", 103 INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", 104 INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", 105 INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", 106 INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", 107 INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", 108 INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", 109 INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", 110 INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", 111 INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", 112 INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", 113 INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", 114 INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", 115 INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", 116 INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", 117 INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", 118 INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", 119 -- INIT_A/INIT_B: Initial values on output port 120 INIT_A => X"000000000", 121 INIT_B => X"000000000", 122 -- INIT_FILE: Optional file used to specify initial RAM contents 123 INIT_FILE => "NONE", 124 -- RSTTYPE: "SYNC" or "ASYNC" 125 RSTTYPE => "SYNC", 126 -- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR" 127 RST_PRIORITY_A => "CE", 128 RST_PRIORITY_B => "CE", 129 -- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE" 130 SIM_COLLISION_CHECK => "ALL", 131 -- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior 132 SIM_DEVICE => "SPARTAN6", 133 -- SRVAL_A/SRVAL_B: Set/Reset value for RAM output 134 SRVAL_A => X"000000000", 135 SRVAL_B => X"000000000", 136 -- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" 137 WRITE_MODE_A => "WRITE_FIRST", 138 WRITE_MODE_B => "WRITE_FIRST" 139 ) 140 port map ( 141 -- Port A Data: 32-bit (each) output Port A data 142 DOA => DOA, 143 -- 32-bit output A port data output 144 DOPA => DOPA, 145 -- 4-bit output A port parity output 146 -- Port B Data: 32-bit (each) output Port B data 147 DOB => DOB, 148 -- 32-bit output B port data output 149 DOPB => DOPB, 150 -- 4-bit output B port parity output 151 -- Port A Address/Control Signals: 14-bit (each) input Port A address and control signals 152 ADDRA => ADDRA, 153 -- 14-bit input A port address input 154 CLKA => CLKA, 155 -- 1-bit input A port clock input 156 ENA => ENA, 157 -- 1-bit input A port enable input 158 REGCEA => REGCEA, -- 1-bit input A port register clock enable input 159 RSTA => RSTA, 160 -- 1-bit input A port register set/reset input 161 WEA => WEA, 162 -- 4-bit input Port A byte-wide write enable input 163 -- Port A Data: 32-bit (each) input Port A data 164 DIA => DIA, 165 -- 32-bit input A port data input 166 DIPA => DIPA, 167 -- 4-bit input A port parity input 168 -- Port B Address/Control Signals: 14-bit (each) input Port B address and control signals 169 ADDRB => ADDRB, 170 -- 14-bit input B port address input 171 CLKB => CLKB, 172 -- 1-bit input B port clock input 173 ENB => ENB, 174 -- 1-bit input B port enable input 175 REGCEB => REGCEB, -- 1-bit input B port register clock enable input 176 RSTB => RSTB, 177 -- 1-bit input B port register set/reset input 178 WEB => WEB, 179 -- 4-bit input Port B byte-wide write enable input 180 -- Port B Data: 32-bit (each) input Port B data 181 DIB => DIB, 182 -- 32-bit input B port data input 183 DIPB => DIPB 184 -- 4-bit input B port parity input 185 ); 186 187end architecture; 188