1User Guide 2========== 3 4OpenROAD is divided into a number of tools that are orchestrated 5together to achieve RTL-to-GDS. As of the current implementation, the 6flow is divided into three stages: 7 81. Logic Synthesis: is performed by `yosys`_. 92. Floorplanning through Detailed Routing: are performed by `OpenROAD App`_. 103. KLayout: GDS merge, DRC and LVS (public PDKs) 11 12To Run OpenROAD flow, we provide scripts to automate the RTL-to-GDS 13stages. Alternatively, you can run the individual steps manually. 14 15**GitHub:** `OpenROAD-flow-scripts`_ 16 17Code Organization 18~~~~~~~~~~~~~~~~~ 19 20This repository serves as an example RTL-to-GDS flow using the OpenROAD tools. 21 22The two main components are: 23 241. **tools**: This directory contains the source code for the entire 25 ``openroad`` app (via submodules) as well as other tools required for 26 the flow. The script ``build_openroad.sh`` in this repository will 27 automatically build the OpenROAD toolchain. 28 292. **flow**: This directory contains reference recipes and scripts to 30 run \| designs through the flow. It also contains platforms and test 31 designs. 32 33Setup 34~~~~~ 35 36The flow has the following dependencies: 37 38- OpenROAD 39- KLayout 40- Yosys 41 42The dependencies can either be obtained from a pre-compiled build export 43or built manually. See the `KLayout website <https://www.klayout.de/>`__ 44for installation instructions. 45 46Using the flow 47~~~~~~~~~~~~~~ 48 49See the flow `README`_ for details about the flow and how to run designs through the flow. 50 51Logic Synthesis 52--------------- 53 54GitHub: https://github.com/The-OpenROAD-Project/yosys 55 56**Setup** 57 58**Requirements** 59 60- C++ compiler with C++11 support (up-to-date CLANG or GCC is 61 recommended) 62- GNU Flex, GNU Bison, and GNU Make. 63- TCL, readline and libffi. 64 65On Ubuntu: 66 67:: 68 69 $ sudo apt-get install build-essential clang bison flex \ 70 libreadline-dev gawk tcl-dev libffi-dev git \ 71 graphviz xdot pkg-config python3 libboost-system-dev \ 72 libboost-python-dev libboost-filesystem-dev zlib1g-dev 73 74On Mac OS X Homebrew can be used to install dependencies (from within 75cloned yosys repository): 76 77:: 78 79 $ brew tap Homebrew/bundle && brew bundle 80 81To configure the build system to use a specific compiler, use one of 82 83:: 84 85 $ make config-clang 86 $ make config-gcc 87 88**Build** 89 90To build Yosys simply type ‘make’ in this directory. 91 92:: 93 94 $ make 95 $ sudo make install 96 97**Synthesis Script** 98 99:: 100 101 yosys -import 102 103 if {[info exist ::env(DC_NETLIST)]} { 104 exec cp $::env(DC_NETLIST) $::env(RESULTS_DIR)/1_1_yosys.v 105 exit 106 } 107 108 # Don't change these unless you know what you are doing 109 set stat_ext "_stat.rep" 110 set gl_ext "_gl.v" 111 set abc_script "+read_constr,$::env(SDC_FILE);strash;ifraig;retime,-D,{D},-M,6;strash;dch,-f;map,-p-M,1,{D},-f;topo;dnsize;buffer,-p;upsize;" 112 113 114 # Setup verilog include directories 115 set vIdirsArgs "" 116 if {[info exist ::env(VERILOG_INCLUDE_DIRS)]} { 117 foreach dir $::env(VERILOG_INCLUDE_DIRS) { 118 lappend vIdirsArgs "-I$dir" 119 } 120 set vIdirsArgs [join $vIdirsArgs] 121 } 122 123 124 # read verilog files 125 foreach file $::env(VERILOG_FILES) { 126 read_verilog -sv {*}$vIdirsArgs $file 127 } 128 129 130 # Read blackbox stubs of standard cells. This allows for standard cell (or 131 # structural netlist) support in the input verilog 132 read_verilog $::env(BLACKBOX_V_FILE) 133 134 # Apply toplevel parameters (if exist) 135 if {[info exist ::env(VERILOG_TOP_PARAMS)]} { 136 dict for {key value} $::env(VERILOG_TOP_PARAMS) { 137 chparam -set $key $value $::env(DESIGN_NAME) 138 } 139 } 140 141 # Read platform specific mapfile for OPENROAD_CLKGATE cells 142 if {[info exist ::env(CLKGATE_MAP_FILE)]} { 143 read_verilog $::env(CLKGATE_MAP_FILE) 144 } 145 146 # Use hierarchy to automatically generate blackboxes for known memory macro. 147 # Pins are enumerated for proper mapping 148 if {[info exist ::env(BLACKBOX_MAP_TCL)]} { 149 source $::env(BLACKBOX_MAP_TCL) 150 } 151 152 # generic synthesis 153 synth -top $::env(DESIGN_NAME) -flatten 154 155 # Optimize the design 156 opt -purge 157 158 # technology mapping of latches 159 if {[info exist ::env(LATCH_MAP_FILE)]} { 160 techmap -map $::env(LATCH_MAP_FILE) 161 } 162 163 # technology mapping of flip-flops 164 dfflibmap -liberty $::env(OBJECTS_DIR)/merged.lib 165 opt 166 167 # Technology mapping for cells 168 abc -D [expr $::env(CLOCK_PERIOD) * 1000] \ 169 -constr "$::env(SDC_FILE)" \ 170 -liberty $::env(OBJECTS_DIR)/merged.lib \ 171 -script $abc_script \ 172 -showtmp 173 174 # technology mapping of constant hi- and/or lo-drivers 175 hilomap -singleton \ 176 -hicell {*}$::env(TIEHI_CELL_AND_PORT) \ 177 -locell {*}$::env(TIELO_CELL_AND_PORT) 178 179 # replace undef values with defined constants 180 setundef -zero 181 182 # Splitting nets resolves unwanted compound assign statements in netlist (assign {..} = {..}) 183 splitnets 184 185 # insert buffer cells for pass through wires 186 insbuf -buf {*}$::env(MIN_BUF_CELL_AND_PORTS) 187 188 # remove unused cells and wires 189 opt_clean -purge 190 191 # reports 192 tee -o $::env(REPORTS_DIR)/synth_check.txt check 193 tee -o $::env(REPORTS_DIR)/synth_stat.txt stat -liberty $::env(OBJECTS_DIR)/merged.lib 194 195 # write synthesized design 196 write_verilog -noattr -noexpr -nohex -nodec $::env(RESULTS_DIR)/1_1_yosys.v 197 198Initialize Floorplan 199-------------------- 200 201:: 202 203 initialize_floorplan 204 [-site site_name] LEF site name for ROWS 205 [-tracks tracks_file] routing track specification 206 -die_area "lx ly ux uy" die area in microns 207 [-core_area "lx ly ux uy"] core area in microns 208 or 209 -utilization util utilization (0-100 percent) 210 [-aspect_ratio ratio] height / width, default 1.0 211 [-core_space space] space around core, default 0.0 (microns) 212 213The die area and core size used to write ROWs can be specified 214explicitly with the -die_area and -core_area arguments. Alternatively, 215the die and core area can be computed from the design size and 216utilization as show below: 217 218If no -tracks file is used the routing layers from the LEF are used. 219 220:: 221 222 core_area = design_area / (utilization / 100) 223 core_width = sqrt(core_area / aspect_ratio) 224 core_height = core_width * aspect_ratio 225 core = ( core_space, core_space ) ( core_space + core_width, core_space + core_height ) 226 die = ( 0, 0 ) ( core_width + core_space * 2, core_height + core_space * 2 ) 227 228Place pins around core boundary. 229 230:: 231 232 auto_place_pins pin_layer 233 234Gate Resizer 235------------ 236 237Gate resizer commands are described below. The resizer commands stop 238when the design area is ``-max_utilization util`` percent of the core 239area. ``util`` is between 0 and 100. 240 241:: 242 243 set_wire_rc [-layer layer_name] 244 [-resistance res ] 245 [-capacitance cap] 246 [-corner corner_name] 247 248The ``set_wire_rc`` command sets the resistance and capacitance used to 249estimate delay of routing wires. Use ``-layer`` or ``-resistance`` and 250``-capacitance``. If ``-layer`` is used, the LEF technology resistance 251and area/edge capacitance values for the layer are used. The units for 252``-resistance`` and ``-capacitance`` are from the first liberty file 253read, resistance_unit/distance_unit and liberty 254capacitance_unit/distance_unit. RC parasitics are added based on placed 255component pin locations. If there are no component locations no 256parasitics are added. The resistance and capacitance are per distance 257unit of a routing wire. Use the ``set_units`` command to check units or 258``set_cmd_units`` to change units. They should represent “average” 259routing layer resistance and capacitance. If the set_wire_rc command is 260not called before resizing, the default_wireload model specified in the 261first liberty file or with the SDC set_wire_load command is used to make 262parasitics. 263 264:: 265 266 buffer_ports [-inputs] 267 [-outputs] 268 -buffer_cell buffer_cell 269 270The ``buffer_ports -inputs`` command adds a buffer between the input and 271its loads. The ``buffer_ports -outputs`` adds a buffer between the port 272driver and the output port. If The default behavior is ``-inputs`` and 273``-outputs`` if neither is specified. 274 275:: 276 277 resize [-libraries resize_libraries] 278 [-dont_use cells] 279 [-max_utilization util] 280 281The ``resize`` command resizes gates to normalize slews. 282 283The ``-libraries`` option specifies which libraries to use when 284resizing. ``resize_libraries`` defaults to all of the liberty libraries 285that have been read. Some designs have multiple libraries with different 286transistor thresholds (Vt) and are used to trade off power and speed. 287Chosing a low Vt library uses more power but results in a faster design 288after the resizing step. Use the ``-dont_use`` option to specify a list 289of patterns of cells to not use. For example, ``*/DLY*`` says do not use 290cells with names that begin with ``DLY`` in all libraries. 291 292:: 293 294 repair_max_cap -buffer_cell buffer_cell 295 [-max_utilization util] 296 repair_max_slew -buffer_cell buffer_cell 297 [-max_utilization util] 298 299The ``repair_max_cap`` and ``repair_max_slew`` commands repair nets with 300maximum capacitance or slew violations by inserting buffers in the net. 301 302:: 303 304 repair_max_fanout -max_fanout fanout 305 -buffer_cell buffer_cell 306 [-max_utilization util] 307 308The ``repair_max_fanout`` command repairs nets with a fanout greater 309than ``fanout`` by inserting buffers between the driver and the loads. 310Buffers are located at the center of each group of loads. 311 312:: 313 314 repair_tie_fanout [-max_fanout fanout] 315 [-verbose] 316 lib_port 317 318The ``repair_tie_fanout`` command repairs tie high/low nets with fanout 319greater than ``fanout`` by cloning the tie high/low driver. ``lib_port`` 320is the tie high/low port, which can be a library/cell/port name or 321object returned by ``get_lib_pins``. Clones are located at the center of 322each group of loads. 323 324:: 325 326 repair_hold_violations -buffer_cell buffer_cell 327 [-max_utilization util] 328 329The ``repair_hold_violations`` command inserts buffers to repair hold 330check violations. 331 332:: 333 334 report_design_area 335 336The ``report_design_area`` command reports the area of the design’s 337components and the utilization. 338 339:: 340 341 report_floating_nets [-verbose] 342 343The ``report_floating_nets`` command reports nets with only one pin 344connection. Use the ``-verbose`` flag to see the net names. 345 346A typical resizer command file is shown below. 347 348:: 349 350 read_lef nlc18.lef 351 read_liberty nlc18.lib 352 read_def mea.def 353 read_sdc mea.sdc 354 set_wire_rc -layer metal2 355 set buffer_cell [get_lib_cell nlc18_worst/snl_bufx4] 356 set max_util 90 357 buffer_ports -buffer_cell $buffer_cell 358 resize -resize 359 repair_max_cap -buffer_cell $buffer_cell -max_utilization $max_util 360 repair_max_slew -buffer_cell $buffer_cell -max_utilization $max_util 361 # repair tie hi/low before max fanout so they don't get buffered 362 repair_tie_fanout -max_fanout 100 Nangate/LOGIC1_X1/Z 363 repair_max_fanout -max_fanout 100 -buffer_cell $buffer_cell -max_utilization $max_util 364 repair_hold_violations -buffer_cell $buffer_cell -max_utilization $max_util 365 366Note that OpenSTA commands can be used to report timing metrics before 367or after resizing the design. 368 369:: 370 371 set_wire_rc -layer metal2 372 report_checks 373 report_tns 374 report_wns 375 report_checks 376 377 resize 378 379 report_checks 380 report_tns 381 report_wns 382 383Timing Analysis 384--------------- 385 386Timing analysis commands are documented in src/OpenSTA/doc/OpenSTA.pdf. 387 388After the database has been read from LEF/DEF, Verilog or an OpenDB 389database, use the ``read_liberty`` command to read Liberty library files 390used by the design. 391 392The example script below timing analyzes a database. 393 394:: 395 396 read_liberty liberty1.lib 397 read_db reg1.db 398 create_clock -name clk -period 10 {clk1 clk2 clk3} 399 set_input_delay -clock clk 0 {in1 in2} 400 set_output_delay -clock clk 0 out 401 report_checks 402 403MacroPlace 404---------- 405 406TritonMacroPlace 407https://github.com/The-OpenROAD-Project/TritonMacroPlace 408 409:: 410 411 macro_placement -global_config <global_config_file> 412 413- **global_config** : Set global config file loction. [string] 414 415Global Config Example 416^^^^^^^^^^^^^^^^^^^^^ 417 418:: 419 420 set ::HALO_WIDTH_V 1 421 set ::HALO_WIDTH_H 1 422 set ::CHANNEL_WIDTH_V 0 423 set ::CHANNEL_WIDTH_H 0 424 425- **HALO_WIDTH_V** : Set macro’s vertical halo. [float; unit: micron] 426- **HALO_WIDTH_H** : Set macro’s horizontal halo. [float; unit: micron] 427- **CHANNEL_WIDTH_V** : Set macro’s vertical channel width. [float; 428 unit: micron] 429- **CHANNEL_WIDTH_H** : Set macro’s horizontal channel width. [float; 430 unit: micron] 431 432Tapcell 433------- 434 435Tapcell and endcap insertion. 436 437:: 438 439 tapcell -tapcell_master <tapcell_master> 440 -endcap_master <endcap_master> 441 -endcap_cpp <endcap_cpp> 442 -distance <dist> 443 -halo_width_x <halo_x> 444 -halo_width_y <halo_y> 445 -tap_nwin2_master <tap_nwin2_master> 446 -tap_nwin3_master <tap_nwin3_master> 447 -tap_nwout2_master <tap_nwout2_master> 448 -tap_nwout3_master <tap_nwout3_master> 449 -tap_nwintie_master <tap_nwintie_master> 450 -tap_nwouttie_master <tap_nwouttie_master> 451 -cnrcap_nwin_master <cnrcap_nwin_master> 452 -cnrcap_nwout_master <cnrcap_nwout_master> 453 -incnrcap_nwin_master <incnrcap_nwin_master> 454 -incnrcap_nwout_master <incnrcap_nwout_master> 455 -tbtie_cpp <tbtie_cpp> 456 -no_cell_at_top_bottom 457 -add_boundary_cell 458 459You can find script examples for supported technologies 460``tap/etc/scripts`` 461 462Global Placement 463---------------- 464 465RePlAce global placement. 466https://github.com/The-OpenROAD-Project/RePlAce 467 468:: 469 470 global_placement -skip_initial_place 471 -incremental 472 -bin_grid_count <grid_count> 473 -density <density> 474 -init_density_penalty <init_density_penalty> 475 -init_wirelength_coef <init_wirelength_coef> 476 -min_phi_coef <min_phi_coef> 477 -max_phi_coef <max_phi_coef> 478 -overflow <overflow> 479 -initial_place_max_iter <max_iter> 480 -initial_place_max_fanout <max_fanout> 481 -verbose_level <level> 482 483Flow Control 484^^^^^^^^^^^^ 485 486- **skip_initial_place** : Skip the initial placement (BiCGSTAB 487 solving) before Nesterov placement. IP improves HPWL by ~5% on large 488 designs. Equal to ‘-initial_place_max_iter 0’ 489- **incremental** : Enable the incremental global placement. Users 490 would need to tune other parameters (e.g. init_density_penalty) with 491 pre-placed solutions. 492 493Tuning Parameters 494^^^^^^^^^^^^^^^^^ 495 496- **bin_grid_count** : Set bin grid’s counts. Default: Defined by 497 internal algorithm. [64,128,256,512,…, int] 498- **density** : Set target density. Default: 0.70 [0-1, float] 499- **init_density_penalty** : Set initial density penalty. Default: 8e-5 500 [1e-6 - 1e6, float] 501- \__init_wire_length__coef_\_ : Set initial wirelength coefficient. 502 Default: 0.25 [unlimited, float] 503- **min_phi_coef** : Set pcof_min(µ_k Lower Bound). Default: 0.95 504 [0.95-1.05, float] 505- **max_phi_coef** : Set pcof_max(µ_k Upper Bound). Default: 1.05 506 [1.00-1.20, float] 507- **overflow** : Set target overflow for termination condition. 508 Default: 0.1 [0-1, float] 509- **initial_place_max_iter** : Set maximum iterations in initial place. 510 Default: 20 [0-, int] 511- **initial_place_max_fanout** : Set net escape condition in initial 512 place when ‘fanout >= initial_place_max_fanout’. Default: 200 [1-, 513 int] 514 515Other Options 516^^^^^^^^^^^^^ 517 518- **verbose_level** : Set verbose level for RePlAce. Default: 1 [0-10, 519 int] 520 521Detailed Placement 522------------------ 523 524Legalize a design that has been globally placed. 525 526:: 527 528 legalize_placement [-constraints constraints_file] 529 530Clock Tree Synthesis 531-------------------- 532 533Create clock tree subnets. 534 535:: 536 537 clock_tree_synthesis -root_buf <root_buf> \ 538 -buf_list <tree_bufs> \ 539 [-clk_nets <list_of_clk_nets>] 540 541- ``root_buffer`` is the master cell of the buffer that serves as root 542- ``buf_list`` is the list of master cells of the buffers that can be used 543 for building the clock tree. 544- ``clk_nets`` is a string containing the names of the clock roots. If 545 this parameter is ommitted, TritonCTS looks for the clock roots 546 automatically. 547 548Global Routing 549-------------- 550 551FastRoute global route. Generate routing guides given a placed design. 552 553:: 554 555 fastroute -output_file out_file 556 -capacity_adjustment <cap_adjust> 557 -min_routing_layer <min_layer> 558 -max_routing_layer <max_layer> 559 -pitches_in_tile <pitches> 560 -layers_adjustments <list_of_layers_to_adjust> 561 -regions_adjustments <list_of_regions_to_adjust> 562 -nets_alphas_priorities <list_of_alphas_per_net> 563 -verbose <verbose> 564 -unidirectional_routing 565 -clock_net_routing 566 567Options description: 568 569- **capacity_adjustment**: Set global capacity adjustment (e.g.: 570 -capacity_adjustment *0.3*) 571 572- **min_routing_layer**: Set minimum routing layer (e.g.: 573 -min_routing_layer *2*) 574 575- **max_routing_layer**: Set maximum routing layer (e.g.: 576 max_routing_layer *9*) 577 578- **pitches_in_tile**: Set the number of pitches inside a GCell 579 580- **layers_adjustments**: Set capacity adjustment to specific layers 581 (e.g.: -layers_adjustments {{ } …}) 582 583- **regions_adjustments**: Set capacity adjustment to specific regions 584 (e.g.: -regions_adjustments { } …}) 585 586- **nets_alphas_priorities**: Set alphas for specific nets when using 587 clock net routing (e.g.: -nets_alphas_priorities {{ } …}) 588 589- **verbose**: Set verbose of report. 0 for less verbose, 1 for medium 590 verbose, 2 for full verbose (e.g.: -verbose 1) 591 592- **unidirectional_routing**: Activate unidirectional routing *(flag)* 593 594- **clock_net_routing**: Activate clock net routing *(flag)* 595 596- **NOTE 1:** if you use the flag *unidirectional_routing*, the minimum 597 routing layer will be assigned as “2” automatically 598 599- **NOTE 2:** the first routing layer of the design have index equal to 600 1 601 602- **NOTE 3:** if you use the flag *clock_net_routing*, only guides for 603 clock nets will be generated 604 605Detailed Routing 606---------------- 607 608**Run** 609 610:: 611 612 detailed_route -param <param_file> 613 614Options description: 615 616- **param_file**: This file contains the parameters used to 617 control the detailed router) 618 619.. _`OpenROAD-flow-scripts`: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts 620.. _`yosys`: https://github.com/The-OpenROAD-Project/yosys 621.. _`OpenROAD App`: https://github.com/The-OpenROAD-Project/OpenROAD 622.. _`README`: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/README.md 623