1module top (in1, in2, clk1, clk2, clk3, out); 2 input in1, in2, clk1, clk2, clk3; 3 output out; 4 wire r1q, r2q, u1z, u2z; 5 6 DFF_X1 r1 (.D(in1), .CK(clk1), .Q(r1q)); 7 DFF_X1 r2 (.D(in2), .CK(clk2), .Q(r2q)); 8 BUF_X1 u1 (.A(r2q), .Z(u1z)); 9 AND2_X1 u2 (.A1(r1q), .A2(u1z), .ZN(u2z)); 10 DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out)); 11endmodule // top 12