1.model tmp_circuit
2.inputs n1 n2 n3 n4
3.outputs n17
4.clock clk
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6.gate AND2_X1 A1=n1 A2=n2 ZN=t1
7.gate AND2_X1 A1=n3 A2=n4 ZN=t2
8.mlatch DFF_X1 D=t3 Q=n17 QN=dummy_0 clk
9.gate OR2_X1 A1=t1 A2=t2 ZN=t3
10.end
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