1# OpenTimer shell commands to gate-size a design with six NAND2 cells 2# and report timing/power/area values. 3# 4# How to run: ../../bin/ot-shell < sizer.conf 5 6# initialize the design 7# the Nangate has X1, X2, and X3 for teh NAND2 cell 8read_celllib NangateOpenCellLibrary_typical.lib 9read_verilog sizer.v 10read_spef sizer.spef 11read_sdc sizer.sdc 12report_timing 13report_tns 14report_wns 15report_area 16report_leakage_power 17 18# downsize all gates from X2 to X1 19repower_gate inst_0 NAND2_X1 20repower_gate inst_1 NAND2_X1 21repower_gate inst_2 NAND2_X1 22repower_gate inst_3 NAND2_X1 23repower_gate inst_4 NAND2_X1 24repower_gate inst_5 NAND2_X1 25report_timing 26report_tns 27report_wns 28report_area 29report_leakage_power 30 31# upsize all gates from X1 to X4 32repower_gate inst_0 NAND2_X4 33repower_gate inst_1 NAND2_X4 34repower_gate inst_2 NAND2_X4 35repower_gate inst_3 NAND2_X4 36repower_gate inst_4 NAND2_X4 37repower_gate inst_5 NAND2_X4 38report_timing 39report_tns 40report_wns 41report_area 42report_leakage_power 43 44# dump the newest verilog and spef 45dump_verilog -o sizer_opt.v -name sizer_opt 46dump_spef -o sizer_opt.spef 47 48