1# Verilog - Verilog Perl Interface
2# See copyright, etc in below POD section.
3######################################################################
4
5package Verilog::Netlist::Cell;
6
7use Verilog::Netlist;
8use Verilog::Netlist::Subclass;
9use vars qw($VERSION @ISA);
10use strict;
11@ISA = qw(Verilog::Netlist::Cell::Struct
12	Verilog::Netlist::Subclass);
13
14$VERSION = '3.478';
15
16structs('new',
17	'Verilog::Netlist::Cell::Struct'
18	=>[name     	=> '$', #'	# Instantiation name
19	   filename 	=> '$', #'	# Filename this came from
20	   lineno	=> '$', #'	# Linenumber this came from
21	   userdata	=> '%',		# User information
22	   attributes	=> '%', #'	# Misc attributes for systemperl or other processors
23	   #
24	   comment	=> '$', #'	# Comment provided by user
25	   submodname	=> '$', #'	# Which module it instantiates
26	   module	=> '$', #'	# Module reference
27	   params	=> '$', #'	# Textual description of parameters
28	   range	=> '$', #'	# Range of ranged instance
29	   _pins	=> '%',		# List of Verilog::Netlist::Pins
30	   byorder 	=> '$',		# True if Cell call uses order based pins
31	   # after link():
32	   submod	=> '$', #'	# Sub Module reference
33	   gateprim	=> '$', #'	# Primitive (and/buf/cmos etc), but not UDPs
34	   # system perl
35	   _autoinst	=> '$', #'	# Marked with AUTOINST tag
36	   ]);
37
38sub delete {
39    my $self = shift;
40    foreach my $pinref ($self->pins_sorted) {
41	$pinref->delete;
42    }
43    my $h = $self->module->_cells;
44    delete $h->{$self->name};
45    return undef;
46}
47
48######################################################################
49#### Methods
50
51sub logger {
52    my $self = shift;
53    return $self->netlist->logger;
54}
55sub netlist {
56    my $self = shift;
57    return $self->module->netlist;
58}
59
60sub _link_guts {
61    my $self = shift;
62    # This function is HOT, keep simple
63    if (!$self->submod) {
64	if (my $name = $self->submodname) {
65	    my $netlist = $self->netlist;
66	    my $sm = $netlist->find_module_or_interface_for_cell($name);
67	    if (!$sm) {
68		my $name2 = $netlist->remove_defines($name);
69		$sm = $netlist->find_module_or_interface_for_cell($name2)
70		    if $name ne $name2;
71	    }
72	    if ($sm) {
73		$self->submod($sm);
74		$sm->is_top(0);
75	    }
76	}
77    }
78}
79sub _link {
80    my $self = shift;
81    # This function is HOT, keep simple
82    $self->_link_guts();
83    if (!$self->submod && Verilog::Language::is_gateprim($self->submodname)) {
84	$self->gateprim(1);
85    }
86    if (!$self->submod()
87	&& !$self->gateprim
88	&& !$self->module->is_libcell()
89	&& $self->netlist->{link_read}
90	&& !$self->netlist->{_missing_submod}{$self->submodname}
91	) {
92	print "  Link_Read ",$self->submodname,"\n" if $Verilog::Netlist::Debug;
93	# Try 1: Direct filename
94	$self->netlist->read_file(filename=>$self->submodname, error_self=>0);
95	$self->_link_guts();
96	#
97	# Try 2: Libraries
98	if (!$self->submod()) {
99	    $self->netlist->read_libraries();
100	    $self->_link_guts();
101	}
102	# Try 3: Bitch about missing file
103	if (!$self->submod()) {
104	    $self->netlist->read_file(filename=>$self->submodname,
105				      error_self=>($self->netlist->{link_read_nonfatal} ? 0:$self));
106	}
107	# Still missing
108	if (!$self->submod()) {
109	    # Don't link this file again - speeds up if many common gate-ish missing primitives
110	    $self->netlist->{_missing_submod}{$self->submodname} = 1;
111	}
112	# Note if got it the new_module will add it to the _need_link list
113    }
114    # Link pins after module resolved, so don't do it multiple times if not found
115    foreach my $pinref ($self->pins) {
116	$pinref->_link();
117    }
118}
119
120sub lint {
121    my $self = shift;
122    if (!$self->submod() && !$self->gateprim && !$self->netlist->{link_read_nonfatal}) {
123        $self->error($self,"Module/Program/Interface reference not found: ",$self->submodname(),,"\n");
124    }
125    if ($self->netlist->{use_vars}) {
126	foreach my $pinref ($self->pins) {
127	    $pinref->lint();
128	}
129    }
130}
131
132sub verilog_text {
133    my $self = shift;
134    my @out = $self->submodname;
135    if ($self->params) {
136	push @out, " #(".$self->params.")";
137    }
138    push @out, " ".$self->name;
139    if ($self->range) {
140	push @out, " ".$self->range;
141    }
142    push @out, " (";
143    my $comma="";
144    foreach my $pinref ($self->pins_sorted) {
145	push @out, $comma if $comma; $comma=", ";
146	push @out, $pinref->verilog_text;
147    }
148    push @out, ");";
149    return (wantarray ? @out : join('',@out));
150}
151
152sub dump {
153    my $self = shift;
154    my $indent = shift||0;
155    my $norecurse = shift;
156    print " "x$indent,"Cell:",$self->name(),"  is-a:",$self->submodname();
157    print " ".$self->params if (($self->params||"") ne "");
158    print "\n";
159    if ($self->submod()) {
160	$self->submod->dump($indent+10, 'norecurse');
161    }
162    if (!$norecurse) {
163	foreach my $pinref ($self->pins_sorted) {
164	    $pinref->dump($indent+2);
165	}
166    }
167}
168
169######################################################################
170#### Pins
171
172sub new_pin {
173    my $self = shift;
174    # @_ params
175    # Create a new pin under this cell
176    push @_, (cell=>$self);
177    my $pinref = new Verilog::Netlist::Pin(@_);
178    $self->_pins($pinref->name(), $pinref);
179    return $pinref;
180}
181
182sub find_pin {
183    my $self = shift;
184    my $name = shift;
185    return $self->_pins($name) || $self->_pins("\\".$name." ");
186}
187
188sub pins {
189    return (values %{$_[0]->_pins});
190}
191
192sub pins_sorted {
193    return (sort {$a->name() cmp $b->name()} (values %{$_[0]->_pins}));
194}
195
196######################################################################
197#### Package return
1981;
199__END__
200
201=pod
202
203=head1 NAME
204
205Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist
206
207=head1 SYNOPSIS
208
209  use Verilog::Netlist;
210
211  ...
212  my $cell = $module->find_cell('cellname');
213  print $cell->name;
214
215=head1 DESCRIPTION
216
217A Verilog::Netlist::Cell object is created by Verilog::Netlist for every
218instantiation in the current module.
219
220=head1 ACCESSORS
221
222See also Verilog::Netlist::Subclass for additional accessors and methods.
223
224=over 4
225
226=item $self->comment
227
228Returns any comments following the definition.  keep_comments=>1 must be
229passed to Verilog::Netlist::new for comments to be retained.
230
231=item $self->delete
232
233Delete the cell from the module it's under.
234
235=item $self->gateprim
236
237True if the cell is a gate primitive instantiation (buf/cmos/etc), but not
238a UDP.
239
240=item $self->module
241
242Pointer to the module the cell is in.
243
244=item $self->name
245
246The instantiation name of the cell.
247
248=item $self->netlist
249
250Reference to the Verilog::Netlist the cell is under.
251
252=item $self->pins
253
254List of Verilog::Netlist::Pin connections for the cell.
255
256=item $self->pins_sorted
257
258List of name sorted Verilog::Netlist::Pin connections for the cell.
259
260=item $self->range
261
262The range for the cell (e.g. "[1:0]") or false (i.e. undef or "") if not
263ranged.
264
265=item $self->submod
266
267Reference to the Verilog::Netlist::Module the cell instantiates.  Only
268valid after the design is linked.
269
270=item $self->submodname
271
272The module name the cell instantiates (under the cell).
273
274=back
275
276=head1 MEMBER FUNCTIONS
277
278See also Verilog::Netlist::Subclass for additional accessors and methods.
279
280=over 4
281
282=item $self->lint
283
284Checks the cell for errors.  Normally called by Verilog::Netlist::lint.
285
286=item $self->new_pin
287
288Creates a new Verilog::Netlist::Pin connection for this cell.
289
290=item $self->pins_sorted
291
292Returns all Verilog::Netlist::Pin connections for this cell.
293
294=item $self->dump
295
296Prints debugging information for this cell.
297
298=back
299
300=head1 DISTRIBUTION
301
302Verilog-Perl is part of the L<https://www.veripool.org/> free Verilog EDA
303software tool suite.  The latest version is available from CPAN and from
304L<https://www.veripool.org/verilog-perl>.
305
306Copyright 2000-2021 by Wilson Snyder.  This package is free software; you
307can redistribute it and/or modify it under the terms of either the GNU
308Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
309
310=head1 AUTHORS
311
312Wilson Snyder <wsnyder@wsnyder.org>
313
314=head1 SEE ALSO
315
316L<Verilog-Perl>,
317L<Verilog::Netlist::Subclass>
318L<Verilog::Netlist>
319
320=cut
321