1.. Copyright 2003-2021 by Wilson Snyder. 2.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 3 4verilator Arguments 5=================== 6 7The following are the arguments that may be passed to the "verilator" 8executable. 9 10Summary: 11 12 .. include:: ../_build/gen/args_verilator.rst 13 14 15.. option:: <file.v> 16 17 Specifies the Verilog file containing the top module to be Verilated. 18 19.. option:: <file.c/.cc/.cpp/.cxx> 20 21 Used with :vlopt:`--exe` to specify optional C++ files to be linked in 22 with the Verilog code. The file path should either be absolute, or 23 relative to where the make will be executed from, or add to your 24 makefile's VPATH the appropriate directory to find the file. 25 26 See also :vlopt:`-CFLAGS` and :vlopt:`-LDFLAGS` options, which are 27 useful when the C++ files need special compiler flags. 28 29.. option:: <file.a/.o/.so> 30 31 Specifies optional object or library files to be linked in with the 32 Verilog code, as a shorthand for :vlopt:`-LDFLAGS \<file\> 33 <-LDFLAGS>`. The file path should either be absolute, or relative to 34 where the make will be executed from, or add to your makefile's VPATH 35 the appropriate directory to find the file. 36 37 If any files are specified in this way, Verilator will include a make 38 rule that uses these files when linking the module's executable. This 39 generally is only useful when used with the :vlopt:`--exe` option. 40 41.. option:: +1364-1995ext+<ext> 42 43.. option:: +1364-2001ext+<ext> 44 45.. option:: +1364-2005ext+<ext> 46 47.. option:: +1800-2005ext+<ext> 48 49.. option:: +1800-2009ext+<ext> 50 51.. option:: +1800-2012ext+<ext> 52 53.. option:: +1800-2017ext+<ext> 54 55 Specifies the language standard to be used with a specific filename 56 extension, <ext>. 57 58 For compatibility with other simulators, see also the synonyms 59 :vlopt:`+verilog1995ext+\<ext\>`, :vlopt:`+verilog2001ext+\<ext\>`, and 60 :vlopt:`+systemverilogext+\<ext\>`. 61 62 For any source file, the language specified by these options takes 63 precedence over any language specified by the 64 :vlopt:`--default-language` or :vlopt:`--language` options. 65 66 These options take effect in the order they are encountered. Thus the 67 following would use Verilog 1995 for ``a.v`` and Verilog 2001 for 68 ``b.v``: 69 70 .. code-block:: bash 71 72 verilator ... +1364-1995ext+v a.v +1364-2001ext+v b.v 73 74 These options are only recommended for legacy mixed language designs, as 75 the preferable option is to edit the code to repair new keywords, or add 76 appropriate ```begin_keywords``. 77 78 .. note:: 79 80 ```begin_keywords`` is a SystemVerilog construct, which specifies 81 *only* the set of keywords to be recognized. This also controls some 82 error messages that vary between language standards. Note at present 83 Verilator tends to be overly permissive, e.g. it will accept many 84 grammar and other semantic extensions which might not be legal when 85 set to an older standard. 86 87.. option:: --assert 88 89 Enable all assertions. 90 91.. option:: --autoflush 92 93 After every $display or $fdisplay, flush the output stream. This 94 ensures that messages will appear immediately but may reduce 95 performance. For best performance call :code:`fflush(stdout)` 96 occasionally in the C++ main loop. Defaults to off, which will buffer 97 output as provided by the normal C/C++ standard library IO. 98 99.. option:: --bbox-sys 100 101 Black box any unknown $system task or function calls. System tasks will 102 simply become no-operations, and system functions will be replaced with 103 unsized zero. Arguments to such functions will be parsed, but not 104 otherwise checked. This prevents errors when linting in the presence of 105 company specific PLI calls. 106 107 Using this argument will likely cause incorrect simulation. 108 109.. option:: --bbox-unsup 110 111 Black box some unsupported language features, currently UDP tables, the 112 cmos and tran gate primitives, deassign statements, and mixed edge 113 errors. This may enable linting the rest of the design even when 114 unsupported constructs are present. 115 116 Using this argument will likely cause incorrect simulation. 117 118.. option:: --bin <filename> 119 120 Rarely needed. Override the default filename for Verilator itself. 121 When a dependency (.d) file is created, this filename will become a 122 source dependency, such that a change in this binary will have make 123 rebuild the output files. 124 125.. option:: --build 126 127 After generating the SystemC/C++ code, Verilator will invoke the 128 toolchain to build the model library (and executable when :vlopt:`--exe` 129 is also used). Verilator manages the build itself, and for this --build 130 requires GNU Make to be available on the platform. 131 132.. option:: -CFLAGS <flags> 133 134 Add specified C compiler argument to the generated makefiles. For 135 multiple flags either pass them as a single argument with space 136 separators quoted in the shell (:command:`-CFLAGS "-a -b"`), or use 137 multiple -CFLAGS options (:command:`-CFLAGS -a -CFLAGS -b`). 138 139 When make is run on the generated makefile these will be passed to the 140 C++ compiler (g++/clang++/msvc++). 141 142.. option:: --cc 143 144 Specifies C++ without SystemC output mode; see also :vlopt:`--sc` 145 option. 146 147.. option:: --cdc 148 149 Permanently experimental. Perform some clock domain crossing checks and 150 issue related warnings (CDCRSTLOGIC) and then exit; if warnings other 151 than CDC warnings are needed make a second run with 152 :vlopt:`--lint-only`. Additional warning information is also written to 153 the file :file:`<prefix>__cdc.txt`. 154 155 Currently only checks some items that other CDC tools missed; if you 156 have interest in adding more traditional CDC checks, please contact the 157 authors. 158 159.. option:: --clk <signal-name> 160 161 With :vlopt:`--clk`, the specified signal-name is taken as a root clock 162 into the model; Verilator will mark the signal as clocker and 163 propagate the clocker attribute automatically to other signals downstream in 164 that clock tree. 165 166 The provided signal-name is specified using a RTL hierarchy path. For 167 example, v.foo.bar. If the signal is the input to top-module, then 168 directly provide the signal name. Alternatively, use a 169 :option:`/*verilator&32;clocker*/` metacomment in RTL file to mark the 170 signal directly. 171 172 If clock signals are assigned to vectors and then later used as 173 individual bits, Verilator will attempt to decompose the vector and 174 connect the single-bit clock signals. 175 176 The clocker attribute is useful in cases where Verilator does not 177 properly distinguish clock signals from other data signals. Using 178 clocker will cause the signal indicated to be considered a clock, and 179 remove it from the combinatorial logic reevaluation checking code. This 180 may greatly improve performance. 181 182.. option:: --compiler <compiler-name> 183 184 Enables workarounds for the specified C++ compiler (list below). 185 Currently this does not change any performance tuning options, but it may 186 in the future. 187 188 clang 189 Tune for clang. This may reduce execution speed as it enables several 190 workarounds to avoid silly hard-coded limits in clang. This includes 191 breaking deep structures as for msvc as described below. 192 193 gcc 194 Tune for GNU C++, although generated code should work on almost any 195 compliant C++ compiler. Currently the default. 196 197 msvc 198 Tune for Microsoft Visual C++. This may reduce execution speed as it 199 enables several workarounds to avoid silly hard-coded limits in 200 MSVC++. This includes breaking deeply nested parenthesized 201 expressions into sub-expressions to avoid error C1009, and breaking 202 deep blocks into functions to avoid error C1061. 203 204.. option:: --converge-limit <loops> 205 206 Rarely needed. Specifies the maximum number of runtime iterations 207 before creating a model failed to converge error. Defaults to 100. 208 209.. option:: --coverage 210 211 Enables all forms of coverage, alias for :vlopt:`--coverage-line` 212 :vlopt:`--coverage-toggle` :vlopt:`--coverage-user`. 213 214.. option:: --coverage-line 215 216 Enables basic block line coverage analysis. See :ref:`Line Coverage`. 217 218.. option:: --coverage-max-width <width> 219 220 Rarely needed. Specify the maximum bit width of a signal that is 221 subject to toggle coverage. Defaults to 256, as covering large vectors 222 may greatly slow coverage simulations. 223 224.. option:: --coverage-toggle 225 226 Enables adding signal toggle coverage. See :ref:`Toggle Coverage`. 227 228.. option:: --coverage-underscore 229 230 Enable coverage of signals that start with an underscore. Normally, 231 these signals are not covered. See also :vlopt:`--trace-underscore` 232 option. 233 234.. option:: --coverage-user 235 236 Enables adding user inserted functional coverage. See :ref:`User Coverage`. 237 238.. option:: -D<var>=<value> 239 240 Defines the given preprocessor symbol. Similar to :vlopt:`+define 241 <+define+<var>>`, but does not allow multiple definitions with a single 242 option using plus signs. "+define" is fairly standard across Verilog 243 tools while "-D" is similar to :command:`gcc -D`. 244 245.. option:: --debug 246 247 Run under debug. 248 249 * Select the debug executable of Verilator (if available), this 250 generally is a less-optimized binary with symbols present (so GDB can be used on it). 251 * Enable debugging messages (equivalent to :vlopt:`--debugi 3 <--debugi>`). 252 * Enable internal assertions (equivalent to :vlopt:`--debug-check`). 253 * Enable intermediate form dump files (equivalent to :vlopt:`--dump-treei 3 254 <--dump-treei>`). 255 * Leak to make node numbers unique (equivalent to :vlopt:`--debug-leak 256 <--no-debug-leak>`. 257 * Call abort() instead of exit() if there are any errors (so GDB can see 258 the program state). 259 260.. option:: --debug-check 261 262 Rarely needed. Enable internal debugging assertion checks, without 263 changing debug verbosity. Enabled automatically with :vlopt:`--debug` 264 option. 265 266.. option:: --no-debug-leak 267 268 In :vlopt:`--debug` mode, by default Verilator intentionally leaks 269 AstNode instances instead of freeing them, so that each node pointer is 270 unique in the resulting tree files and dot files. 271 272 This option disables the leak. This may avoid out-of-memory errors when 273 Verilating large models in :vlopt:`--debug` mode. 274 275 Outside of :vlopt:`--debug` mode, AstNode instances should never be 276 leaked and this option has no effect. 277 278.. option:: --debugi <level> 279 280 Rarely needed - for developer use. Set internal debugging level 281 globally to the specified debug level (1-10). Higher levels produce more 282 detailed messages. 283 284.. option:: --debugi-<srcfile> <level> 285 286 Rarely needed - for developer use. Set the specified Verilator source 287 file to the specified level (e.g. :vlopt:`--debugi-V3Width 9 288 <--debugi>`). Higher levels produce more detailed messages. See 289 :vlopt:`--debug` for other implications of enabling debug. 290 291.. option:: --default-language <value> 292 293 Select the language to be used by default when first processing each 294 Verilog file. The language value must be "VAMS", "1364-1995", 295 "1364-2001", "1364-2001-noconfig", "1364-2005", "1800-2005", 296 "1800-2009", "1800-2012", "1800-2017", or "1800+VAMS". 297 298 Any language associated with a particular file extension (see the 299 various +<lang>*\ ext+ options) will be used in preference to the 300 language specified by :vlopt:`--default-language`. 301 302 The :vlopt:`--default-language` is only recommended for legacy code 303 using the same language in all source files, as the preferable option is 304 to edit the code to repair new keywords, or add appropriate 305 :code:`\`begin_keywords`. For legacy mixed language designs, the various 306 ``+<lang>ext+`` options should be used. 307 308 If no language is specified, either by this option or ``+<lang>ext+`` 309 options, then the latest SystemVerilog language (IEEE 1800-2017) is 310 used. 311 312.. option:: +define+<var>=<value> 313 314.. option:: +define+<var>=<value>[+<var2>=<value2>][...] 315 316 Defines the given preprocessor symbol, or multiple symbols if separated 317 by plus signs. Similar to :vlopt:`-D <-D<var>>`; +define is fairly 318 standard across Verilog tools while :vlopt:`-D <-D<var>>` is similar to 319 :command:`gcc -D`. 320 321.. option:: --dpi-hdr-only 322 323 Only generate the DPI header file. This option has no effect on the 324 name or location of the emitted DPI header file, it is output in 325 :vlopt:`--Mdir` as it would be without this option. 326 327.. option:: --dump-defines 328 329 With :vlopt:`-E`, suppress normal output, and instead print a list of 330 all defines existing at the end of pre-processing the input 331 files. Similar to GCC "-dM" option. This also gives you a way of finding 332 out what is predefined in Verilator using the command: 333 334 .. code-block:: bash 335 336 touch foo.v ; verilator -E --dump-defines foo.v 337 338.. option:: --dump-tree 339 340 Rarely needed. Enable writing .tree debug files with dumping level 3, 341 which dumps the standard critical stages. For details on the format see 342 the Verilator Internals manual. :vlopt:`--dump-tree` is enabled 343 automatically with :vlopt:`--debug`, so :vlopt:`--debug --no-dump-tree 344 <--dump-tree>` may be useful if the dump files are large and not 345 desired. 346 347.. option:: --dump-treei <level> 348 349.. option:: --dump-treei-<srcfile> <level> 350 351 Rarely needed - for developer use. Set internal tree dumping level 352 globally to a specific dumping level or set the specified Verilator 353 source file to the specified tree dumping level (e.g. 354 :vlopt:`--dump-treei-V3Order 9 <--dump-treei>`). Level 0 disables dumps 355 and is equivalent to :vlopt:`--no-dump-tree <--dump-tree>`. Level 9 356 enables dumping of every stage. 357 358.. option:: --dump-tree-addrids 359 360 Rarely needed - for developer use. Replace AST node addresses with 361 short identifiers in tree dumps to enhance readability. Each unique 362 pointer value is mapped to a unique identifier, but note that this is 363 not necessarily unique per node instance as an address might get reused 364 by a newly allocated node after a node with the same address has been 365 dumped then freed. 366 367.. option:: -E 368 369 Preprocess the source code, but do not compile, similar to C++ 370 preprocessing using :command:`gcc -E`. Output is written to standard 371 out. Beware of enabling debugging messages, as they will also go to 372 standard out. 373 374 See also :vlopt:`--dump-defines`, :vlopt:`-P`, and 375 :vlopt:`--pp-comments` options. 376 377.. option:: --error-limit <value> 378 379 After this number of errors are encountered during Verilator run, exit. 380 Warnings are not counted in this limit. Defaults to 50. 381 382 Does not affect simulation runtime errors, for those see 383 :vlopt:`+verilator+error+limit+\<value\>`. 384 385.. option:: --exe 386 387 Generate an executable. You will also need to pass additional .cpp 388 files on the command line that implement the main loop for your 389 simulation. 390 391.. option:: --expand-limit <value> 392 393 Rarely needed. Fine-tune optimizations to set the maximum size of an 394 expression in 32-bit words to expand into separate word-based 395 statements. 396 397.. option:: -F <file> 398 399 Read the specified file, and act as if all text inside it was specified 400 as command line arguments. Any relative paths are relative to the 401 directory containing the specified file. See also :vlopt:`-f` 402 option. Note :option:`-F` is fairly standard across Verilog tools. 403 404.. option:: -f <file> 405 406 Read the specified file, and act as if all text inside it was specified 407 as command line arguments. Any relative paths are relative to the 408 current directory. See also :vlopt:`-F` option. Note :option:`-f` is 409 fairly standard across Verilog tools. 410 411 The file may contain :code:`//` comments which are ignored to the end of 412 the line. It may also contain :code:`/* .. */` comments which are 413 ignored, be cautious that wildcards are not handled in -f files, and 414 that :code:`directory/*` is the beginning of a comment, not a wildcard. 415 Any :code:`$VAR`, :code:`$(VAR)`, or :code:`${VAR}` will be replaced 416 with the specified environment variable. 417 418.. option:: -FI <file> 419 420 Force include of the specified C++ header file. All generated C++ files 421 will insert a #include of the specified file before any other 422 includes. The specified file might be used to contain define prototypes 423 of custom :code:`VL_VPRINTF` functions, and may need to include 424 :file:`verilatedos.h` as this file is included before any other standard 425 includes. 426 427.. option:: --flatten 428 429 Force flattening of the design's hierarchy, with all modules, tasks and 430 functions inlined. Typically used with :vlopt:`--xml-only`. Note 431 flattening large designs may require significant CPU time, memory and 432 storage. 433 434.. option:: -G<name>=<value> 435 436 Overwrites the given parameter of the toplevel module. The value is 437 limited to basic data literals: 438 439 Verilog integer literals 440 The standard Verilog integer literals are supported, so values like 441 32'h8, 2'b00, 4 etc. are allowed. Care must be taken that the single 442 quote (I') is properly escaped in an interactive shell, e.g., 443 as :code:`-GWIDTH=8'hx`. 444 445 C integer literals 446 It is also possible to use C integer notation, including hexadecimal 447 (0x..), octal (0..) or binary (0b..) notation. 448 449 Double literals 450 Double literals must be one of the following styles: 451 - contains a dot (.) (e.g. 1.23) 452 - contains an exponent (e/E) (e.g. 12e3) 453 - contains p/P for hexadecimal floating point in C99 (e.g. 0x123.ABCp1) 454 455 Strings 456 Strings must be in double quotes (""). They must be escaped properly 457 on the command line, e.g. as :code:`-GSTR="\"My String\""` or 458 :code:`-GSTR='"My String"'`. 459 460.. option:: --gate-stmts <value> 461 462 Rarely needed. Set the maximum number of statements that may be present 463 in an equation for the gate substitution optimization to inline that 464 equation. 465 466.. option:: --gdb 467 468 Run Verilator underneath an interactive GDB (or VERILATOR_GDB 469 environment variable value) session. See also :vlopt:`--gdbbt` option. 470 471.. option:: --gdbbt 472 473 If :vlopt:`--debug` is specified, run Verilator underneath a GDB process 474 and print a backtrace on exit, then exit GDB immediately. Without 475 :vlopt:`--debug` or if GDB doesn't seem to work, this flag is ignored. 476 Intended for easy creation of backtraces by users; otherwise see the 477 :vlopt:`--gdb` option. 478 479.. option:: --generate-key 480 481 Generate a true-random key suitable for use with :vlopt:`--protect-key`, 482 print it, and exit immediately. 483 484.. option:: --getenv <variable> 485 486 If the variable is declared in the environment, print it and exit 487 immediately. Otherwise, if it's built into Verilator 488 (e.g. VERILATOR_ROOT), print that and exit immediately. Otherwise, print 489 a newline and exit immediately. This can be useful in makefiles. See 490 also :vlopt:`-V`, and the various :file:`*.mk` files. 491 492.. option:: --help 493 494 Displays this message and program version and exits. 495 496.. option:: --hierarchical 497 498 Enable hierarchical Verilation otherwise 499 :option:`/*verilator&32;hier_block*/` metacomment is ignored. See 500 :ref:`Hierarchical Verilation`. 501 502.. option:: -I<dir> 503 504 See :vlopt:`-y`. 505 506.. option:: --if-depth <value> 507 508 Rarely needed. Set the depth at which the IFDEPTH warning will fire, 509 defaults to 0 which disables this warning. 510 511.. option:: +incdir+<dir> 512 513 See :vlopt:`-y`. 514 515.. option:: --inline-mult <value> 516 517 Tune the inlining of modules. The default value of 2000 specifies that up 518 to 2000 new operations may be added to the model by inlining, if more than 519 this number of operations would result, the module is not inlined. Larger 520 values, or a value < 1 will inline everything, will lead to longer compile 521 times, but potentially faster simulation speed. This setting is ignored 522 for very small modules; they will always be inlined, if allowed. 523 524.. option:: --instr-count-dpi <value> 525 526 Assumed dynamic instruction count of the average DPI import. This is used 527 by the partitioning algorithm when creating a multithread model. The 528 default value is 200. Adjusting this to an appropriate value can yield 529 performance improvements in multithreaded models. Ignored when creating a 530 single threaded model. 531 532.. option:: -j [<value>] 533 534 Specify the level of parallelism for :vlopt:`--build`. The <value> must 535 be a positive integer specifying the maximum number of parallel build 536 jobs, or can be omitted. When <value> is omitted, the build will not try 537 to limit the number of parallel build jobs but attempt to execute all 538 independent build steps in parallel. 539 540.. option:: -LDFLAGS <flags> 541 542 Add specified C linker arguments to the generated makefiles. For multiple 543 flags either pass them as a single argument with space separators quoted 544 in the shell (``-LDFLAGS "-a -b"``), or use multiple -LDFLAGS arguments 545 (``-LDFLAGS -a -LDFLAGS -b``). 546 547 When make is run on the generated makefile these will be passed to the 548 C++ linker (ld) **after** the primary file being linked. This flag is 549 called :vlopt:`-LDFLAGS` as that's the traditional name in simulators; 550 it's would have been better called LDLIBS as that's the Makefile 551 variable it controls. (In Make, LDFLAGS is before the first object, 552 LDLIBS after. -L libraries need to be in the Make variable LDLIBS, not 553 LDFLAGS.) 554 555.. option:: --l2-name <value> 556 557 Instead of using the module name when showing Verilog scope, use the 558 name provided. This allows simplifying some Verilator-embedded modeling 559 methodologies. Default is an l2-name matching the top module. The 560 default before Verilator 3.884 was ``--l2-name v``. 561 562 For example, the program :code:`module t; initial $display("%m"); 563 endmodule` will show by default "t". With ``--l2-name v`` it will print 564 "v". 565 566.. option:: --language <value> 567 568 A synonym for :vlopt:`--default-language`, for compatibility with other 569 tools and earlier versions of Verilator. 570 571.. option:: +libext+<ext>[+<ext>][...] 572 573 Specify the extensions that should be used for finding modules. If for 574 example module "my" is referenced, look in :file:`my.<ext>`. Note 575 "+libext+" is fairly standard across Verilog tools. Defaults to 576 ".v+.sv". 577 578.. option:: --lib-create <name> 579 580 Produces C++, Verilog wrappers and a Makefile which can in turn produce 581 a DPI library which can be used by Verilator or other simulators along 582 with the corresponding Verilog wrapper. The Makefile will build both a 583 static and dynamic version of the library named :file:`lib<name>.a` and 584 :file:`lib<name>.so` respectively. This is done because some simulators 585 require a dynamic library, but the static library is arguably easier to 586 use if possible. :vlopt:`--protect-lib` implies :vlopt:`--protect-ids`. 587 588 When using :vlopt:`--lib-create` it is advised to also use 589 :vlopt:`--timescale-override /1fs <--timescale-override>` to ensure the 590 model has a time resolution that is always compatible with the time 591 precision of the upper instantiating module. 592 593 See also :vlopt:`--protect-lib`. 594 595.. option:: --lint-only 596 597 Check the files for lint violations only, do not create any other 598 output. 599 600 You may also want the :vlopt:`-Wall` option to enable messages that are 601 considered stylistic and not enabled by default. 602 603 If the design is not to be completely Verilated see also the 604 :vlopt:`--bbox-sys` and :vlopt:`--bbox-unsup` options. 605 606.. option:: --make <build-tool> 607 608 Generates a script for the specified build tool. 609 610 Supported values are ``gmake`` for GNU Make and ``cmake`` for CMake. 611 Both can be specified together. If no build tool is specified, gmake is 612 assumed. The executable of gmake can be configured via environment 613 variable "MAKE". 614 615 When using :vlopt:`--build` Verilator takes over the responsibility of 616 building the model library/executable. For this reason :option:`--make` 617 cannot be specified when using :vlopt:`--build`. 618 619.. option:: -MAKEFLAGS <string> 620 621 When using :vlopt:`--build`, add the specified argument to the invoked 622 make command line. For multiple flags either pass them as a single 623 argument with space separators quoted in the shell (e.g. ``-MAKEFLAGS 624 "-a -b"``), or use multiple -MAKEFLAGS arguments 625 (e.g. ``-MAKEFLAGS -l -MAKEFLAGS -k``). Use of this option should not be 626 required for simple builds using the host toolchain. 627 628.. option:: --max-num-width <value> 629 630 Set the maximum number literal width (e.g. in 1024'd22 this it the 631 1024). Defaults to 64K. 632 633.. option:: --MMD =item --no-MMD 634 635 Enable/disable creation of .d dependency files, used for make dependency 636 detection, similar to gcc -MMD option. By default this option is 637 enabled for :vlopt:`--cc` or :vlopt:`--sc` modes. 638 639.. option:: --MP 640 641 When creating .d dependency files with :vlopt:`--MMD` option, make phony 642 targets. Similar to :command:`gcc -MP` option. 643 644.. option:: --Mdir <directory> 645 646 Specifies the name of the Make object directory. All generated files 647 will be placed in this directory. If not specified, "obj_dir" is used. 648 The directory is created if it does not exist and the parent directories 649 exist; otherwise manually create the Mdir before calling Verilator. 650 651.. option:: --no-merge-const-pool 652 653 Rarely needed. In order to minimize cache footprint, values of different 654 data type, that are yet emitted identically in C++ are merged in the 655 constant pool. This option disables this and causes every constant pool 656 entry with a distinct data type to be emitted separately. 657 658.. option:: --mod-prefix <topname> 659 660 Specifies the name to prepend to all lower level classes. Defaults to 661 the same as :vlopt:`--prefix`. 662 663.. option:: --no-clk <signal-name> 664 665 Prevent the specified signal from being marked as clock. See 666 :vlopt:`--clk`. 667 668.. option:: --no-decoration 669 670 When creating output Verilated code, minimize comments, white space, 671 symbol names and other decorative items, at the cost of greatly reduced 672 readability. This may assist C++ compile times. This will not typically 673 change the ultimate model's performance, but may in some cases. 674 675.. option:: --no-pins64 676 677 Backward compatible alias for :vlopt:`--pins-bv 33 <--pins-bv>`. 678 679.. option:: --no-skip-identical =item --skip-identical 680 681 Rarely needed. Disables or enables skipping execution of Verilator if 682 all source files are identical, and all output files exist with newer 683 dates. By default this option is enabled for :vlopt:`--cc` or 684 :vlopt:`--sc` modes only. 685 686.. option:: +notimingchecks 687 688 Ignored for compatibility with other simulators. 689 690.. option:: -O0 691 692 Disables optimization of the model. 693 694.. option:: -O3 695 696 Enables slow optimizations for the code Verilator itself generates (as 697 opposed to :vlopt:`-CFLAGS -O3 <-CFLAGS>` which effects the C compiler's 698 optimization. :vlopt:`-O3` may improve simulation performance at the 699 cost of compile time. This currently sets :vlopt:`--inline-mult -1 700 <--inline-mult>`. 701 702.. option:: -O<optimization-letter> 703 704 Rarely needed. Enables or disables a specific optimizations, with the 705 optimization selected based on the letter passed. A lowercase letter 706 disables an optimization, an upper case letter enables it. This is 707 intended for debugging use only; see the source code for 708 version-dependent mappings of optimizations to -O letters. 709 710.. option:: -o <executable> 711 712 Specify the name for the final executable built if using :vlopt:`--exe`. 713 Defaults to the :vlopt:`--prefix` if not specified. 714 715.. option:: --no-order-clock-delay 716 717 Rarely needed. Disables a bug fix for ordering of clock enables with 718 delayed assignments. This option should only be used when suggested by 719 the developers. 720 721.. option:: --output-split <statements> 722 723 Enables splitting the output .cpp files into multiple outputs. When a 724 C++ file exceeds the specified number of operations, a new file will be 725 created at the next function boundary. In addition, if the total output 726 code size exceeds the specified value, VM_PARALLEL_BUILDS will be set to 727 1 by default in the generated make files, making parallel compilation 728 possible. Using :vlopt:`--output-split` should have only a trivial 729 impact on model performance. But can greatly improve C++ compilation 730 speed. The use of "ccache" (set for you if present at configure time) is 731 also more effective with this option. 732 733 This option is on by default with a value of 20000. To disable, pass with a 734 value of 0. 735 736.. option:: --output-split-cfuncs <statements> 737 738 Enables splitting functions in the output .cpp files into multiple 739 functions. When a generated function exceeds the specified number of 740 operations, a new function will be created. With 741 :vlopt:`--output-split`, this will enable the C++ compiler to compile 742 faster, at a small loss in performance that gets worse with decreasing 743 split values. Note that this option is stronger than 744 :vlopt:`--output-split` in the sense that :vlopt:`--output-split` will 745 not split inside a function. 746 747 Defaults to the value of :vlopt:`--output-split`, unless explicitly 748 specified. 749 750.. option:: --output-split-ctrace <statements> 751 752 Similar to :vlopt:`--output-split-cfuncs`, enables splitting trace 753 functions in the output .cpp files into multiple functions. 754 755 Defaults to the value of :vlopt:`--output-split`, unless explicitly 756 specified. 757 758.. option:: -P 759 760 With :vlopt:`-E`, disable generation of :code:`&96;line` markers and 761 blank lines, similar to :command:`gcc -P`. 762 763.. option:: --pins64 764 765 Backward compatible alias for :vlopt:`--pins-bv 65 <--pins-bv>`. Note 766 that's a 65, not a 64. 767 768.. option:: --pins-bv <width> 769 770 Specifies SystemC inputs/outputs of greater than or equal to <width> 771 bits wide should use sc_bv's instead of uint32/vluint64_t's. The 772 default is "--pins-bv 65", and the value must be less than or equal 773 to 65. Versions before Verilator 3.671 defaulted to "--pins-bv 33". 774 The more sc_bv is used, the worse for performance. Use the 775 :option:`/*verilator&32;sc_bv*/` metacomment to select specific ports to 776 be sc_bv. 777 778.. option:: --pins-sc-uint 779 780 Specifies SystemC inputs/outputs of greater than 2 bits wide should use 781 sc_uint between 2 and 64. When combined with the 782 :vlopt:`--pins-sc-biguint` combination, it results in sc_uint being used 783 between 2 and 64 and sc_biguint being used between 65 and 512. 784 785.. option:: --pins-sc-biguint 786 787 Specifies SystemC inputs/outputs of greater than 65 bits wide should use 788 sc_biguint between 65 and 512, and sc_bv from 513 upwards. When 789 combined with the :vlopt:`--pins-sc-uint` combination, it results in 790 sc_uint being used between 2 and 64 and sc_biguint being used between 65 791 and 512. 792 793.. option:: --pins-uint8 794 795 Specifies SystemC inputs/outputs that are smaller than the 796 :vlopt:`--pins-bv` setting and 8 bits or less should use uint8_t instead 797 of uint32_t. Likewise pins of width 9-16 will use uint16_t instead of 798 uint32_t. 799 800.. option:: --pipe-filter <command> 801 802 Rarely needed. Verilator will spawn the specified command as a 803 subprocess pipe, to allow the command to perform custom edits on the 804 Verilog code before it reaches Verilator. 805 806 Before reading each Verilog file, Verilator will pass the file name to 807 the subprocess' stdin with :code:`read "<filename>"`. The filter may 808 then read the file and perform any filtering it desires, and feeds the 809 new file contents back to Verilator on stdout by first emitting a line 810 defining the length in bytes of the filtered output 811 :code:`Content-Length: <bytes>`, followed by the new filtered 812 contents. Output to stderr from the filter feeds through to Verilator's 813 stdout and if the filter exits with non-zero status Verilator 814 terminates. See the file:`t/t_pipe_filter` test for an example. 815 816 To debug the output of the filter, try using the :vlopt:`-E` option to 817 see preprocessed output. 818 819.. option:: --pp-comments 820 821 With :vlopt:`-E`, show comments in preprocessor output. 822 823.. option:: --prefix <topname> 824 825 Specifies the name of the top level class and makefile. Defaults to V 826 prepended to the name of the :vlopt:`--top` option, or V prepended to 827 the first Verilog filename passed on the command line. 828 829.. option:: --prof-c 830 831 When compiling the C++ code, enable the compiler's profiling flag 832 (e.g. :code:`g++ -pg`). See :ref:`Profiling`. 833 834 Using :vlopt:`--prof-cfuncs` also enables :vlopt:`--prof-c`. 835 836.. option:: --prof-cfuncs 837 838 Modify the created C++ functions to support profiling. The functions 839 will be minimized to contain one "basic" statement, generally a single 840 always block or wire statement. (Note this will slow down the 841 executable by ~5%.) Furthermore, the function name will be suffixed 842 with the basename of the Verilog module and line number the statement 843 came from. This allows gprof or oprofile reports to be correlated with 844 the original Verilog source statements. See :ref:`Profiling`. 845 846 Using :vlopt:`--prof-cfuncs` also enables :vlopt:`--prof-c`. 847 848.. option:: --prof-threads 849 850 Enable gantt chart data collection for threaded builds. See :ref:`Thread 851 Profiling` and :ref:`Thread PGO`. 852 853.. option:: --protect-key <key> 854 855 Specifies the private key for :vlopt:`--protect-ids`. For best security 856 this key should be 16 or more random bytes, a reasonable secure choice 857 is the output of :command:`verilator --generate-key` . Typically, a key 858 would be created by the user once for a given protected design library, 859 then every Verilator run for subsequent versions of that library would 860 be passed the same :vlopt:`--protect-key`. Thus, if the input Verilog is 861 similar between library versions (Verilator runs), the Verilated code 862 will likewise be mostly similar. 863 864 If :vlopt:`--protect-key` is not specified and a key is needed, 865 Verilator will generate a new key for every Verilator run. As the key is 866 not saved, this is best for security, but means every Verilator run will 867 give vastly different output even for identical input, perhaps harming 868 compile times (and certainly thrashing any "ccache"). 869 870.. option:: --protect-ids 871 872 Hash any private identifiers (variable, module, and assertion block 873 names that are not on the top level) into hashed random-looking 874 identifiers, resulting after compilation in protected library binaries 875 that expose less design information. This hashing uses the provided or 876 default :vlopt:`--protect-key`, see important details there. 877 878 Verilator will also create a :file:`<prefix>__idmap.xml` file which 879 contains the mapping from the hashed identifiers back to the original 880 identifiers. This idmap file is to be kept private, and is to assist 881 mapping any simulation runtime design assertions, coverage, or trace 882 information, which will report the hashed identifiers, back to the 883 original design's identifier names. 884 885 Using DPI imports/exports is allowed and generally relatively safe in 886 terms of information disclosed, which is limited to the DPI function 887 prototyptes. Use of the VPI is not recommended as many design details 888 may be exposed, and an INSECURE warning will be issued. 889 890.. option:: --protect-lib <name> 891 892 Produces a DPI library similar to :vlopt:`--lib-create`, but hides 893 internal design details. :vlopt:`--protect-lib` implies 894 :vlopt:`--protect-ids`, and :vlopt:`--lib-create`. 895 896 This allows for the secure delivery of sensitive IP without the need for 897 encrypted RTL (i.e. IEEE P1735). See :file:`examples/make_protect_lib` 898 in the distribution for a demonstration of how to build and use the DPI 899 library. 900 901.. option:: --private 902 903 Opposite of :vlopt:`--public`. Is the default; this option exists for 904 backwards compatibility. 905 906.. option:: --public 907 908 This is only for historical debug use. Using it may result in 909 mis-simulation of generated clocks. 910 911 Declares all signals and modules public. This will turn off signal 912 optimizations as if all signals had a :option:`/*verilator&32;public*/` 913 metacomments and inlining. This will also turn off inlining as if all 914 modules had a :option:`/*verilator&32;public_module*/`, unless the 915 module specifically enabled it with 916 :option:`/*verilator&32;inline_module*/`. 917 918.. option:: --public-flat-rw 919 920 Declares all variables, ports and wires public as if they had 921 :code:`/*verilator public_flat_rw @ 922 (<variable's_source_process_edge>)*/` metacomments. This will make them 923 VPI accessible by their flat name, but not turn off module inlining. 924 This is particularly useful in combination with :vlopt:`--vpi`. This may 925 also in some rare cases result in mis-simulation of generated clocks. 926 Instead of this global option, marking only those signals that need 927 public_flat_rw is typically significantly better performing. 928 929.. option:: -pvalue+<name>=<value> 930 931 Overwrites the given parameter(s) of the toplevel module. See :vlopt:`-G 932 <-G<name>>` for a detailed description. 933 934.. option:: --quiet-exit 935 936 When exiting due to an error, do not display the "Exiting due to Errors" 937 nor "Command Failed" messages. 938 939.. option:: --relative-includes 940 941 When a file references an include file, resolve the filename relative to 942 the path of the referencing file, instead of relative to the current 943 directory. 944 945.. option:: --reloop-limit 946 947 Rarely needed. Verilator attempts to turn some common sequences of 948 statements into loops in the output. This argument specifies the minimum 949 number of iterations the resulting loop needs to have in order to perform 950 this transformation. Default limit is 40. A smaller number may slightly 951 improve C++ compilation time on designs where these sequences are common, 952 however effect on model performance requires benchmarking. 953 954.. option:: --report-unoptflat 955 956 Extra diagnostics for UNOPTFLAT warnings. This includes for each loop, 957 the 10 widest variables in the loop, and the 10 most fanned out 958 variables in the loop. These are candidates for splitting into multiple 959 variables to break the loop. 960 961 In addition produces a GraphViz DOT file of the entire strongly 962 connected components within the source associated with each loop. This 963 is produced irrespective of whether :vlopt:`--dump-tree` is set. Such 964 graphs may help in analyzing the problem, but can be very large indeed. 965 966 Various commands exist for viewing and manipulating DOT files. For 967 example the "dot" command can be used to convert a DOT file to a PDF for 968 printing. For example: 969 970 .. code-block:: bash 971 972 dot -Tpdf -O Vt_unoptflat_simple_2_35_unoptflat.dot 973 974 will generate a PDF :file:`Vt_unoptflat_simple_2_35_unoptflat.dot.pdf` 975 from the DOT file. 976 977 As an alternative, the :command:`xdot` command can be used to view DOT 978 files interactively: 979 980 .. code-block:: bash 981 982 xdot Vt_unoptflat_simple_2_35_unoptflat.dot 983 984.. option:: --rr 985 986 Run Verilator and record with the :command:`rr` command. See: 987 rr-project.org. 988 989.. option:: --savable 990 991 Enable including save and restore functions in the generated model. See 992 :ref:`Save/Restore`. 993 994.. option:: --sc 995 996 Specifies SystemC output mode; see also :vlopt:`--cc` option. 997 998.. option:: --stats 999 1000 Creates a dump file with statistics on the design in 1001 :file:`<prefix>__stats.txt`. 1002 1003.. option:: --stats-vars 1004 1005 Creates more detailed statistics, including a list of all the variables 1006 by size (plain :vlopt:`--stats` just gives a count). See 1007 :vlopt:`--stats`, which is implied by this. 1008 1009.. option:: --structs-packed 1010 1011 Converts all unpacked structures to packed structures and issues a 1012 UNPACKED warning. Currently this is the default and 1013 :vlopt:`--no-structs-packed <--structs-packed>` will not work. 1014 Specifying this option allows for forward compatibility when a future 1015 version of Verilator no longer always packs unpacked structures. 1016 1017.. option:: -sv 1018 1019 Specifies SystemVerilog language features should be enabled; equivalent 1020 to :vlopt:`--language 1800-2017 <--language>`. This option is selected 1021 by default, it exists for compatibility with other simulators. 1022 1023.. option:: +systemverilogext+<ext> 1024 1025 A synonym for :vlopt:`+1800-2017ext+\<ext\>`. 1026 1027.. option:: --threads <threads> 1028 1029.. option:: --no-threads 1030 1031 With "--threads 0" or "--no-threads", the default, the generated model 1032 is not thread safe. With "--threads 1", the generated model is single 1033 threaded but may run in a multithreaded environment. With "--threads N", 1034 where N >= 2, the model is generated to run multithreaded on up to N 1035 threads. See :ref:`Multithreading`. 1036 1037.. option:: --threads-dpi all 1038 1039.. option:: --threads-dpi none 1040 1041.. option:: --threads-dpi pure 1042 1043 When using :vlopt:`--threads`, controls which DPI imported tasks and 1044 functions are considered thread safe. 1045 1046 With "--threads-dpi all", 1047 Enable Verilator to assume all DPI imports are threadsafe, and to use 1048 thread-local storage for communication with DPI, potentially improving 1049 performance. Any DPI libraries need appropriate mutexes to avoid 1050 undefined behavior. 1051 1052 With "--threads-dpi none", 1053 Verilator assume DPI imports are not thread safe, and Verilator will 1054 serialize calls to DPI imports by default, potentially harming 1055 performance. 1056 1057 With "--threads-dpi pure", the default, 1058 Verilator assumes DPI pure imports are threadsafe, but non-pure DPI 1059 imports are not. 1060 1061 See also :vlopt:`--instr-count-dpi` option. 1062 1063.. option:: --threads-max-mtasks <value> 1064 1065 Rarely needed. When using :vlopt:`--threads`, specify the number of 1066 mtasks the model is to be partitioned into. If unspecified, Verilator 1067 approximates a good value. 1068 1069.. option:: --timescale <timeunit>/<timeprecision> 1070 1071 Sets default timescale, timeunit and timeprecision for when "`timescale" 1072 does not occur before a given module. Default is "1ps/1ps" (to match 1073 SystemC). This is overridden by :vlopt:`--timescale-override`. 1074 1075.. option:: --timescale-override <timeunit>/<timeprecision> 1076 1077.. option:: --timescale-override /<timeprecision> 1078 1079 Overrides all "\`timescale"s in sources. The timeunit may be left empty 1080 to specify only to override the timeprecision, e.g. "/1fs". 1081 1082 The time precision must be consistent with SystemC's 1083 "sc_set_time_resolution()", or the C++ code instantiating the Verilated 1084 module. As "1fs" is the finest time precision it may be desirable to 1085 always use a precision of "1fs". 1086 1087.. option:: --top <topname> 1088 1089.. option:: --top-module <topname> 1090 1091 When the input Verilog contains more than one top level module, 1092 specifies the name of the Verilog module to become the top level module, 1093 and sets the default for :vlopt:`--prefix` if not explicitly specified. 1094 This is not needed with standard designs with only one top. See also 1095 :option:`MULTITOP` warning. 1096 1097.. option:: --trace 1098 1099 Adds waveform tracing code to the model using VCD format. This overrides 1100 :vlopt:`--trace-fst`. 1101 1102 Verilator will generate additional :file:`<prefix>__Trace*.cpp` files 1103 that will need to be compiled. In addition :file:`verilated_vcd_sc.cpp` 1104 (for SystemC traces) or :file:`verilated_vcd_c.cpp` (for both) must be 1105 compiled and linked in. If using the Verilator generated Makefiles, 1106 these files will be added to the source file lists for you. If you are 1107 not using the Verilator Makefiles, you will need to add these to your 1108 Makefile manually. 1109 1110 Having tracing compiled in may result in some small performance losses, 1111 even when tracing is not turned on during model execution. 1112 1113 See also :vlopt:`--trace-threads` option. 1114 1115.. option:: --trace-coverage 1116 1117 With :vlopt:`--trace` and ``--coverage-*``, enable tracing to include a 1118 traced signal for every :vlopt:`--coverage-line` or 1119 :vlopt:`--coverage-user`\ -inserted coverage point, to assist in 1120 debugging coverage items. Note :vlopt:`--coverage-toggle` does not get 1121 additional signals added, as the original signals being toggle-analyzed 1122 are already visible. 1123 1124 The added signal will be a 32-bit value which will increment on each 1125 coverage occurrence. Due to this, this option may greatly increase trace 1126 file sizes and reduce simulation speed. 1127 1128.. option:: --trace-depth <levels> 1129 1130 Specify the number of levels deep to enable tracing, for example 1131 :vlopt:`--trace-depth 1 <--trace-depth>` to only see the top level's 1132 signals. Defaults to the entire model. Using a small number will 1133 decrease visibility, but greatly improve simulation performance and 1134 trace file size. 1135 1136.. option:: --trace-fst 1137 1138 Enable FST waveform tracing in the model. This overrides 1139 :vlopt:`--trace`. See also :vlopt:`--trace-threads` option. 1140 1141.. option:: --trace-max-array *depth* 1142 1143 Rarely needed. Specify the maximum array depth of a signal that may be 1144 traced. Defaults to 32, as tracing large arrays may greatly slow traced 1145 simulations. 1146 1147.. option:: --trace-max-width *width* 1148 1149 Rarely needed. Specify the maximum bit width of a signal that may be 1150 traced. Defaults to 256, as tracing large vectors may greatly slow 1151 traced simulations. 1152 1153.. option:: --no-trace-params 1154 1155 Disable tracing of parameters. 1156 1157.. option:: --trace-structs 1158 1159 Enable tracing to show the name of packed structure, union, and packed 1160 array fields, rather than a single combined packed bus. Due to VCD file 1161 format constraints this may result in significantly slower trace times 1162 and larger trace files. 1163 1164.. option:: --trace-threads *threads* 1165 1166 Enable waveform tracing using separate threads. This is typically faster 1167 in simulation runtime but uses more total compute. This option is 1168 independent of, and works with, both :vlopt:`--trace` and 1169 :vlopt:`--trace-fst`. Different trace formats can take advantage of 1170 more trace threads to varying degrees. Currently VCD tracing can utilize 1171 at most "--trace-threads 1", and FST tracing can utilize at most 1172 "--trace-threads 2". This overrides :vlopt:`--no-threads` . 1173 1174.. option:: --trace-underscore 1175 1176 Enable tracing of signals or modules that start with an 1177 underscore. Normally, these signals are not output during tracing. See 1178 also :vlopt:`--coverage-underscore` option. 1179 1180.. option:: -U<var> 1181 1182 Undefines the given preprocessor symbol. 1183 1184.. option:: --unroll-count <loops> 1185 1186 Rarely needed. Specifies the maximum number of loop iterations that may be 1187 unrolled. See also :option:`BLKLOOPINIT` warning. 1188 1189.. option:: --unroll-stmts *statements* 1190 1191 Rarely needed. Specifies the maximum number of statements in a loop for 1192 that loop to be unrolled. See also :option:`BLKLOOPINIT` warning. 1193 1194.. option:: --unused-regexp *regexp* 1195 1196 Rarely needed. Specifies a simple regexp with \* and ? that if a signal 1197 name matches will suppress the UNUSED warning. Defaults to 1198 "\*unused\*". Setting it to "" disables matching. 1199 1200.. option:: -V 1201 1202 Shows the verbose version, including configuration information compiled 1203 into Verilator. (Similar to :command:`perl -V`.) See also 1204 :vlopt:`--getenv` option. 1205 1206.. option:: -v *filename* 1207 1208 Read the filename as a Verilog library. Any modules in the file may be 1209 used to resolve instances in the top level module, else ignored. Note 1210 "-v" is fairly standard across Verilog tools. 1211 1212.. option:: --no-verilate 1213 1214 When using :vlopt:`--build`, disable generation of C++/SystemC code, and 1215 execute only the build. This can be useful for rebuilding Verilated code 1216 produced by a previous invocation of Verilator. 1217 1218.. option:: +verilog1995ext+<ext> 1219 1220 Synonym for :vlopt:`+1364-1995ext+\<ext\>`. 1221 1222.. option:: +verilog2001ext+<ext> 1223 1224 Synonym for :vlopt:`+1364-2001ext+\<ext\>`. 1225 1226.. option:: --version 1227 1228 Displays program version and exits. 1229 1230.. option:: --vpi 1231 1232 Enable use of VPI and linking against the :file:`verilated_vpi.cpp` files. 1233 1234.. option:: --waiver-output *filename* 1235 1236 Generate a waiver file which contains all waiver statements to suppress 1237 the warnings emitted during this Verilator run. This in particular is 1238 useful as a starting point for solving linter warnings or suppressing 1239 them systematically. 1240 1241 The generated file is in the Verilator Configuration format, see 1242 :ref:`Configuration Files`, and can directly be consumed by 1243 Verilator. The standard file extension is ".vlt". 1244 1245.. option:: -Wall 1246 1247 Enable all code style warnings, including code style warnings that are 1248 normally disabled by default. Equivalent to :vlopt:`-Wwarn-lint` 1249 :vlopt:`-Wwarn-style`. Excludes some specialty warnings, 1250 i.e. IMPERFECTSCH. 1251 1252.. option:: -Werror-<message> 1253 1254 Promote the specified warning message into an error message. This is 1255 generally to discourage users from violating important site-wide rules, 1256 for example "-Werror-NOUNOPTFLAT". 1257 1258.. option:: -Wfuture-<message> 1259 1260 Rarely needed. Suppress unknown Verilator comments or warning messages 1261 with the given message code. This is used to allow code written with 1262 pragmas for a later version of Verilator to run under a older version; 1263 add "-Wfuture-" arguments for each message code or comment that the new 1264 version supports which the older version does not support. 1265 1266.. option:: -Wno-<message> 1267 1268 Disable the specified warning/error message. This will override any 1269 lint_on directives in the source, i.e. the warning will still not be 1270 printed. 1271 1272.. option:: -Wno-context 1273 1274 Disable showing the suspected context of the warning message by quoting 1275 the source text at the suspected location. This can be used to appease 1276 tools which process the warning messages but may get confused by lines 1277 from the original source. 1278 1279.. option:: -Wno-fatal 1280 1281 When warnings are detected, print them, but do not terminate Verilator. 1282 1283 Having warning messages in builds can be sloppy. It is recommended you 1284 cleanup your code, use inline lint_off, or use ``-Wno-...`` options 1285 rather than using this option. 1286 1287.. option:: -Wno-lint 1288 1289 Disable all lint related warning messages, and all style warnings. This is 1290 equivalent to ``-Wno-ALWCOMBORDER -Wno-BSSPACE -Wno-CASEINCOMPLETE 1291 -Wno-CASEOVERLAP -Wno-CASEX -Wno-CASTCONST -Wno-CASEWITHX -Wno-CMPCONST -Wno-COLONPLUS 1292 -Wno-ENDLABEL -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINCONNECTEMPTY 1293 -Wno-PINMISSING -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED 1294 -Wno-WIDTH`` plus the list shown for Wno-style. 1295 1296 It is strongly recommended you cleanup your code rather than using this 1297 option, it is only intended to be use when running test-cases of code 1298 received from third parties. 1299 1300.. option:: -Wno-style 1301 1302 Disable all code style related warning messages (note by default they are 1303 already disabled). This is equivalent to ``-Wno-DECLFILENAME -Wno-DEFPARAM 1304 -Wno-EOFNEWLINE -Wno-IMPORTSTAR -Wno-INCABSPATH -Wno-PINCONNECTEMPTY 1305 -Wno-PINNOCONNECT -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNUSED 1306 -Wno-VARHIDDEN``. 1307 1308.. option:: -Wpedantic 1309 1310 Warn on any construct demanded by IEEE, and disable all Verilator 1311 extensions that may interfere with IEEE compliance to the standard 1312 defined with :vlopt:`--default-language` (etc). Similar to 1313 :command:`gcc -Wpedantic`. Rarely used, and intended only for strict 1314 compliance tests. 1315 1316.. option:: -Wwarn-<message> 1317 1318 Enables the specified warning message. 1319 1320.. option:: -Wwarn-lint 1321 1322 Enable all lint related warning messages (note by default they are already 1323 enabled), but do not affect style messages. This is equivalent to 1324 ``-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE -Wwarn-CASEINCOMPLETE 1325 -Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASTCONST -Wwarn-CASEWITHX -Wwarn-CMPCONST 1326 -Wwarn-COLONPLUS -Wwarn-ENDLABEL -Wwarn-IMPLICIT -Wwarn-LITENDIAN 1327 -Wwarn-PINMISSING -Wwarn-REALCVT -Wwarn-UNSIGNED -Wwarn-WIDTH``. 1328 1329.. option:: -Wwarn-style 1330 1331 Enable all code style related warning messages. This is equivalent to 1332 ``-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-EOFNEWLINE 1333 -Wwarn-INCABSPATH -Wwarn-PINNOCONNECT -Wwarn-SYNCASYNCNET -Wwarn-UNDRIVEN 1334 -Wwarn-UNUSED -Wwarn-VARHIDDEN``. 1335 1336.. option:: --x-assign 0 1337 1338.. option:: --x-assign 1 1339 1340.. option:: --x-assign fast (default) 1341 1342.. option:: --x-assign unique 1343 1344 Controls the two-state value that is substituted when an explicit X 1345 value is encountered in the source. "--x-assign fast", the default, 1346 converts all Xs to whatever is best for performance. "--x-assign 0" 1347 converts all Xs to 0s, and is also fast. "--x-assign 1" converts all Xs 1348 to 1s, this is nearly as fast as 0, but more likely to find reset bugs 1349 as active high logic will fire. Using "--x-assign unique" will result in 1350 all explicit Xs being replaced by a constant value determined at 1351 runtime. The value is determined by calling a function at initialization 1352 time. This enables randomization of Xs with different seeds on different 1353 executions. This method is the slowest, but safest for finding reset 1354 bugs. 1355 1356 If using "--x-assign unique", you may want to seed your random number 1357 generator such that each regression run gets a different randomization 1358 sequence. The simplest is to use the :vlopt:`+verilator+seed+\<value\>` 1359 runtime option. Alternatively use the system's :code:`srand48()` or for 1360 Windows :code:`srand()` function to do this. You'll probably also want 1361 to print any seeds selected, and code to enable rerunning with that same 1362 seed so you can reproduce bugs. 1363 1364 .. note:: 1365 1366 This option applies only to values which are explicitly written as X 1367 in the Verilog source code. Initial values of clocks are set to 0 1368 unless `--x-initial-edge` is specified. Initial values of all other 1369 state holding variables are controlled with `--x-initial`. 1370 1371.. option:: --x-initial 0 1372 1373.. option:: --x-initial fast 1374 1375.. option:: --x-initial unique (default) 1376 1377 Controls the two-state value that is used to initialize variables that 1378 are not otherwise initialized. 1379 1380 "--x-initial 0", 1381 initializes all otherwise uninitialized variables to zero. 1382 1383 "--x-initial unique", the default, 1384 initializes variables using a function, which determines the value to 1385 use each initialization. This gives greatest flexibility and allows 1386 finding reset bugs. See :ref:`Unknown states`. 1387 1388 "--x-initial fast", 1389 is best for performance, and initializes all variables to a state 1390 Verilator determines is optimal. This may allow further code 1391 optimizations, but will likely hide any code bugs relating to missing 1392 resets. 1393 1394 .. note:: 1395 1396 This option applies only to initial values of variables. Initial 1397 values of clocks are set to 0 unless :vlopt:`--x-initial-edge` is 1398 specified. 1399 1400.. option:: --x-initial-edge 1401 1402 Enables emulation of event driven simulators which generally trigger an 1403 edge on a transition from X to 1 (posedge) or X to 0 (negedge). Thus the 1404 following code, where :code:`rst_n` is uninitialized would set 1405 :code:`res_n` to :code:`1'b1` when :code:`rst_n` is first set to zero: 1406 1407 .. code-block:: sv 1408 1409 reg res_n = 1'b0; 1410 1411 always @(negedge rst_n) begin 1412 if (rst_n == 1'b0) begin 1413 res_n <= 1'b1; 1414 end 1415 end 1416 1417 In Verilator, by default, uninitialized clocks are given a value of 1418 zero, so the above :code:`always` block would not trigger. 1419 1420 While it is not good practice, there are some designs that rely on X 1421 rarr 0 triggering a negedge, particularly in reset sequences. Using 1422 :vlopt:`--x-initial-edge` with Verilator will replicate this 1423 behavior. It will also ensure that X rarr 1 triggers a posedge. 1424 1425 .. note:: 1426 1427 Using this option can affect convergence, andit may be necessary to 1428 use :vlopt:`--converge-limit` to increase the number of convergence 1429 iterations. This may be another indication of problems with the 1430 modeled design that should be addressed. 1431 1432.. option:: --xml-only 1433 1434 Create XML output only, do not create any other output. 1435 1436 The XML format is intended to be used to leverage Verilator's parser and 1437 elaboration to feed to other downstream tools. Be aware that the XML 1438 format is still evolving; there will be some changes in future versions. 1439 1440.. option:: --xml-output <filename> 1441 1442 Filename for XML output file. Using this option automatically sets 1443 :vlopt:`--xml-only`. 1444 1445.. option:: -y <dir> 1446 1447 Add the directory to the list of directories that should be searched for 1448 include files or libraries. The three flags :vlopt:`-y`, 1449 :vlopt:`+incdir+\<dir\>` and :vlopt:`-I\<dir\>` have similar effect; 1450 :vlopt:`+incdir+\<dir\>` and :vlopt:`-y` are fairly standard across 1451 Verilog tools while :vlopt:`-I\<dir\>` is used by many C++ compilers. 1452 1453 Verilator defaults to the current directory "-y ." and any specified 1454 :vlopt:`--Mdir`, though these default paths are used after any user 1455 specified directories. This allows '-y "$(pwd)"' to be used if absolute 1456 filenames are desired for error messages instead of relative filenames. 1457 1458 1459.. _Configuration Files: 1460 1461Configuration Files 1462=================== 1463 1464In addition to the command line, warnings and other features for the 1465:command:`verilator` command may be controlled with configuration files, 1466typically named with the .vlt extension (what makes it a configuration file 1467is the :option:`\`verilator_config` directive). An example: 1468 1469.. code-block:: sv 1470 1471 `verilator_config 1472 lint_off -rule WIDTH 1473 lint_off -rule CASEX -file "silly_vendor_code.v" 1474 1475This disables WIDTH warnings globally, and CASEX for a specific file. 1476 1477Configuration files are fed through the normal Verilog preprocessor prior 1478to parsing, so "\`ifdef", "\`define", and comments may be used as if the 1479configuration file was normal Verilog code. 1480 1481Note that file or line-specific configuration only applies to files read 1482after the configuration file. It is therefore recommended to pass the 1483configuration file to Verilator as the first file. 1484 1485The grammar of configuration commands is as follows: 1486 1487.. option:: `verilator_config 1488 1489 Take remaining text and treat it as Verilator configuration commands. 1490 1491.. option:: coverage_on [-file "<filename>" [-lines <line> [ - <line> ]]] 1492 1493.. option:: coverage_off [-file "<filename>" [-lines <line> [ - <line> ]]] 1494 1495 Enable/disable coverage for the specified filename (or wildcard with 1496 '\*' or '?', or all files if omitted) and range of line numbers (or all 1497 lines if omitted). Often used to ignore an entire module for coverage 1498 analysis purposes. 1499 1500.. option:: clock_enable -module "<modulename>" -var "<signame>" 1501 1502 Indicate the signal is used to gate a clock, and the user takes 1503 responsibility for insuring there are no races related to it. 1504 1505 Same as :option:`/*verilator&32;clock_enable*/` metacomment. 1506 1507.. option:: clocker -module "<modulename>" [-task "<taskname>"] -var "<signame>" 1508 1509.. option:: clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>" 1510 1511.. option:: no_clocker -module "<modulename>" [-task "<taskname>"] -var "<signame>" 1512 1513.. option:: no_clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>" 1514 1515 Indicates that the signal is used as clock or not. This information is 1516 used by Verilator to mark the signal and any derrived signals as 1517 clocker. See :vlopt:`--clk`. 1518 1519 Same as :option:`/*verilator&32;clocker*/` metacomment. 1520 1521.. option:: coverage_block_off -module "<modulename>" -block "<blockname>" 1522 1523.. option:: coverage_block_off -file "<filename>" -line <lineno> 1524 1525 Specifies the entire begin/end block should be ignored for coverage 1526 analysis purposes. Can either be specified as a named block or as a 1527 filename and line number. 1528 1529 Same as :option:`/*verilator&32;coverage_block_off*/` metacomment. 1530 1531.. option:: full_case -file "<filename>" -lines <lineno> 1532 1533.. option:: parallel_case -file "<filename>" -lines <lineno> 1534 1535 Same as :code:`//synopsys full_case` and :code:`//synopsys 1536 parallel_case`. When these synthesis directives are discovered, 1537 Verilator will either formally prove the directive to be true, or 1538 failing that, will insert the appropriate code to detect failing cases 1539 at simulation runtime and print an "Assertion failed" error message. 1540 1541.. option:: hier_block -module "<modulename>" 1542 1543 Specifies that the module is a unit of hierarchical Verilation. Note 1544 that the setting is ignored unless the :vlopt:`--hierarchical` option is 1545 specified. See :ref:`Hierarchical Verilation`. 1546 1547.. option:: inline -module "<modulename>" 1548 1549 Specifies the module may be inlined into any modules that use this 1550 module. Same as :option:`/*verilator&32;inline_module*/` metacomment. 1551 1552.. option:: isolate_assignments -module "<modulename>" [-task "<taskname>"] -var "<signame>" 1553 1554.. option:: isolate_assignments -module "<modulename>" [-function "<funcname>"] -var "<signame>" 1555 1556.. option:: isolate_assignments -module "<modulename>" -function "<fname>" 1557 1558 Used to indicate the assignments to this signal in any blocks should be 1559 isolated into new blocks. When there is a large combinatorial block 1560 that is resulting in an UNOPTFLAT warning, attaching this to the signal 1561 causing a false loop may clear up the problem. 1562 1563 Same as :option:`/*verilator&32;isolate_assignments*/` metacomment. 1564 1565.. option:: no_inline -module "<modulename>" 1566 1567 Specifies the module should not be inlined into any modules that use 1568 this module. Same as :option:`/*verilator&32;no_inline_module*/` 1569 metacomment. 1570 1571.. option:: no_inline [-module "<modulename>"] -task "<taskname>" 1572 1573.. option:: no_inline [-module "<modulename>"] -function "<funcname>" 1574 1575 Specify the function or task should not be inlined into where it is 1576 used. This may reduce the size of the final executable when a task is 1577 used a very large number of times. For this flag to work, the task and 1578 tasks below it must be pure; they cannot reference any variables outside 1579 the task itself. 1580 1581 Same as :option:`/*verilator&32;no_inline_task*/` metacomment. 1582 1583.. option:: lint_on [-rule <message>] [-file "<filename>" [-lines <line> [ - <line>]]] 1584 1585.. option:: lint_off [-rule <message>] [-file "<filename>" [-lines <line> [ - <line>]]] 1586 1587.. option:: lint_off [-rule <message>] [-file "<filename>"] [-match "<string>"] 1588 1589 Enable/disables the specified lint warning, in the specified filename 1590 (or wildcard with '\*' or '?', or all files if omitted) and range of 1591 line numbers (or all lines if omitted). 1592 1593 With lint_off using "\*" will override any lint_on directives in the 1594 source, i.e. the warning will still not be printed. 1595 1596 If the -rule is omitted, all lint warnings (see list in 1597 :vlopt:`-Wno-lint`) are enabled/disabled. This will override all later 1598 lint warning enables for the specified region. 1599 1600 If -match is set the linter warnings are matched against this (wildcard) 1601 string and are waived in case they match and iff rule and file (with 1602 wildcard) also match. 1603 1604 In previous versions -rule was named -msg. The latter is deprecated, but 1605 still works with a deprecation info, it may be removed in future 1606 versions. 1607 1608.. option:: public [-module "<modulename>"] [-task/-function "<taskname>"] -var "<signame>" 1609 1610.. option:: public_flat [-module "<modulename>"] [-task/-function "<taskname>"] -var "<signame>" 1611 1612.. option:: public_flat_rd [-module "<modulename>"] [-task/-function "<taskname>"] -var "<signame>" 1613 1614.. option:: public_flat_rw [-module "<modulename>"] [-task/-function "<taskname>"] -var "<signame>" "@(edge)" 1615 1616 Sets the variable to be public. Same as 1617 :option:`/*verilator&32;public*/` or 1618 :option:`/*verilator&32;public_flat*/`, etc, metacomments. See 1619 e.g. :ref:`VPI Example`. 1620 1621.. option:: profile_data -mtask "<mtask_hash>" -cost <cost_value> 1622 1623 Feeds profile-guided optimization data into the Verilator algorithms in 1624 order to improve model runtime performance. This option is not expected 1625 to be used by users directly. See :ref:`Thread PGO`. 1626 1627.. option:: sc_bv -module "<modulename>" [-task "<taskname>"] -var "<signame>" 1628 1629.. option:: sc_bv -module "<modulename>" [-function "<funcname>"] -var "<signame>" 1630 1631 Sets the port to be of :code:`sc_bv<{width}>` type, instead of bool, 1632 vluint32_t or vluint64_t. Same as :option:`/*verilator&32;sc_bv*/` 1633 metacomment. 1634 1635.. option:: sformat [-module "<modulename>"] [-task "<taskname>"] -var "<signame>" 1636 1637.. option:: sformat [-module "<modulename>"] [-function "<funcname>"] -var "<signame>" 1638 1639 Must be applied to the final argument of type :code:`input string` of a 1640 function or task to indicate the function or task should pass all 1641 remaining arguments through $sformatf. This allows creation of DPI 1642 functions with $display like behavior. See the 1643 :file:`test_regress/t/t_dpi_display.v` file for an example. 1644 1645 Same as :option:`/*verilator&32;sformat*/` metacomment. 1646 1647.. option:: split_var [-module "<modulename>"] [-task "<taskname>"] -var "<varname>" 1648 1649.. option:: split_var [-module "<modulename>"] [-function "<funcname>"] -var "<varname>" 1650 1651 Break the variable into multiple pieces typically to resolve UNOPTFLAT 1652 performance issues. Typically the variables to attach this to are 1653 recommended by Verilator itself, see :option:`UNOPTFLAT`. 1654 1655 Same as :option:`/*verilator&32;split_var*/` metacomment. 1656 1657.. option:: tracing_on [-file "<filename>" [-lines <line> [ - <line> ]]] 1658 1659.. option:: tracing_off [-file "<filename>" [-lines <line> [ - <line> ]]] 1660 1661 Enable/disable waveform tracing for all future signals declared in the 1662 specified filename (or wildcard with '\*' or '?', or all files if 1663 omitted) and range of line numbers (or all lines if omitted). 1664 1665 For tracing_off, instances below any module in the files/ranges 1666 specified will also not be traced. 1667