1// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' 2// 3// Simple bi-directional alias test. 4// 5// This file ONLY is placed under the Creative Commons Public Domain, for 6// any use, without warranty, 2013 by Jeremy Bennett. 7// SPDX-License-Identifier: CC0-1.0 8 9module t (/*AUTOARG*/ 10 // Inputs 11 clk 12 ); 13 input clk; 14 15 // Values to swap and locations for the swapped values. 16 wire [31:0] x_fwd = 32'hdeadbeef; 17 wire [31:0] y_fwd; 18 wire [31:0] x_bwd; 19 wire [31:0] y_bwd = 32'hfeedface; 20 21 swap swap_fwd_i (.a (x_fwd), 22 .b (y_fwd)); 23 swap swap_bwd_i (.a (x_bwd), 24 .b (y_bwd)); 25 26 always @ (posedge clk) begin 27`ifdef TEST_VERBOSE 28 $write ("x_fwd = %x, y_fwd = %x\n", x_fwd, y_fwd); 29 $write ("x_bwd = %x, y_bwd = %x\n", x_bwd, y_bwd); 30`endif 31 if (y_fwd != 32'hefbeadde) $stop; 32 if (x_bwd == 32'hcefaedfe) $stop; 33 $write("*-* All Finished *-*\n"); 34 $finish; 35 end 36 37endmodule 38 39 40// Swap the byte order of two args. 41module swap ( 42 inout wire [31:0] a, 43 inout wire [31:0] b 44 ); 45 46 alias {a[7:0],a[15:8],a[23:16],a[31:24]} = b; 47 48 // Equivalent to 49 50 // wire [31:0] a_prime; 51 // wire [31:0] b_prime; 52 53 // assign b_prime = {a[7:0],a[15:8],a[23:16],a[31:24]}; 54 // assign {a_prime[7:0],a_prime[15:8],a_prime[23:16],a_prime[31:24]} = b; 55 // assign b = b_prime; 56 // assign a = a_prime; 57 58endmodule 59