1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2015 by Jonathon Donaldson. 5// SPDX-License-Identifier: CC0-1.0 6 7module t_bitsel_enum 8 ( 9 output out0, 10 output out1 11 ); 12 13 localparam [6:0] CNST_VAL = 7'h22; 14 15 enum logic [6:0] { 16 ENUM_VAL = 7'h33 17 } MyEnum; 18 19 assign out0 = CNST_VAL[0]; 20 // Not supported by NC-verilog nor VCS, but other simulators do 21 assign out1 = ENUM_VAL[0]; // named values of an enumeration should act like constants so this should work just like the line above works 22 23 initial begin 24 $write("*-* All Finished *-*\n"); 25 $finish; 26 end 27 28endmodule 29