1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2014 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11   input clk;
12
13   integer 	cyc = 0;
14   reg [63:0] 	crc;
15   reg [63:0] 	sum;
16
17   logic [2:0] [1:0] in;
18   always @* in = crc[5:0];
19
20   /*AUTOWIRE*/
21   // Beginning of automatic wires (for undeclared instantiated-module outputs)
22   logic [1:0] [1:0]	out;			// From test of Test.v
23   // End of automatics
24
25   Test test (/*AUTOINST*/
26	      // Outputs
27	      .out			(out/*[1:0][1:0]*/),
28	      // Inputs
29	      .clk			(clk),
30	      .in			(in/*[2:0][1:0]*/));
31
32   // Aggregate outputs into a single result vector
33   wire [63:0] result = {60'h0, out[1],out[0]};
34
35   // Test loop
36   always @ (posedge clk) begin
37`ifdef TEST_VERBOSE
38      $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
39`endif
40      cyc <= cyc + 1;
41      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
42      sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
43      if (cyc==0) begin
44	 // Setup
45	 crc <= 64'h5aef0c8d_d70a4497;
46	 sum <= 64'h0;
47      end
48      else if (cyc<10) begin
49	 sum <= 64'h0;
50      end
51      else if (cyc<90) begin
52      end
53      else if (cyc==99) begin
54	 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
55	 if (crc !== 64'hc77bb9b3784ea091) $stop;
56	 // What checksum will we end up with (above print should match)
57`define EXPECTED_SUM 64'hdc21e42d85441511
58	 if (sum !== `EXPECTED_SUM) $stop;
59	 $write("*-* All Finished *-*\n");
60	 $finish;
61      end
62   end
63
64endmodule
65
66module Test (/*AUTOARG*/
67   // Outputs
68   out,
69   // Inputs
70   clk, in
71   );
72
73   //bug717
74
75   input clk;
76   input logic [2:0][1:0] in;
77
78   output logic [1:0][1:0] out;
79
80   always @(posedge clk) begin
81      out <= in[2 -: 2];
82   end
83endmodule
84