1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2013 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/);
8
9   typedef struct packed {
10      logic [3:2] a;
11      logic [5:4][3:2] b;
12   } ab_t;
13   typedef ab_t [7:6] c_t;  // array of structs
14   typedef struct packed {
15      c_t [17:16] d;
16   } e_t;
17
18`define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
19`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
20
21   initial begin
22      e_t e;
23      `checkh($bits(ab_t),6);
24      `checkh($bits(c_t),12);
25      `checkh($bits(e_t),24);
26      `checkh($bits(e), 24);
27      `checkh($bits(e.d[17]),12);
28      `checkh($bits(e.d[16][6]),6);
29      `checkh($bits(e.d[16][6].b[5]),2);
30      `checkh($bits(e.d[16][6].b[5][2]), 1);
31      //
32      e =        24'b101101010111010110101010;
33      `checkb(e, 24'b101101010111010110101010);
34      e.d[17] =  12'b111110011011;
35      `checkb(e, 24'b111110011011010110101010);
36      e.d[16][6] =                  6'b010101;
37      `checkb(e, 24'b111110011011010110010101);
38      e.d[16][6].b[5] =             2'b10;
39      `checkb(e, 24'b111110011011010110011001);
40      e.d[16][6].b[5][2] =            1'b1;
41      //
42      $write("*-* All Finished *-*\n");
43      $finish;
44   end
45endmodule
46