1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2006 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7`include "verilated.v" 8 9`define STRINGIFY(x) `"x`" 10 11module t (/*AUTOARG*/ 12 // Inputs 13 clk 14 ); 15 16 input clk; 17 18 reg [63:0] crc; 19 integer fd; 20 integer fdtmp; 21 22 t_case_write1_tasks tasks (); 23 24 integer cyc; initial cyc = 0; 25 26 always @ (posedge clk) begin 27 $fwrite(fd, "[%0d] crc=%x ", cyc, crc); 28 tasks.big_case(fd, crc[31:0]); 29 $fwrite(fd, "\n"); 30 end 31 32 always @ (posedge clk) begin 33 //$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); 34 cyc <= cyc + 1; 35 crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; 36 if (cyc==1) begin 37 crc <= 64'h00000000_00000097; 38 $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log\n"}); 39 fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log"}, "w"); 40 fd <= fdtmp; 41 end 42 if (cyc==90) begin 43 $write("*-* All Finished *-*\n"); 44 $finish; 45 end 46 end 47 48endmodule 49