1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7class Cls;
8   int value;
9   extern function int ext_f_np;
10   extern function int ext_f_p();
11   extern function int ext_f_i(int in);
12   extern task ext_t_np;
13   extern task ext_t_p();
14   extern task ext_t_i(int in);
15endclass
16
17function int Cls::ext_f_np;
18   return 1;
19endfunction
20
21function int Cls::ext_f_p();
22   return value;
23endfunction
24
25function int Cls::ext_f_i(int in);
26   return in+1;
27endfunction
28
29task Cls::ext_t_np();
30   $write("*-* All Finished *-*\n");
31endtask
32task Cls::ext_t_p();
33   $finish;
34endtask
35task Cls::ext_t_i(int in);
36   if (in != 2) $stop;
37   value = in;
38endtask
39
40module t (/*AUTOARG*/);
41   initial begin
42      Cls c = new;
43      c.ext_t_i(2);
44      c.ext_t_np();
45      c.ext_t_p();
46      if (c.ext_f_np() != 1) $stop;
47      if (c.ext_f_p() != 2) $stop;
48      if (c.ext_f_i(10) != 11) $stop;
49   end
50endmodule
51