1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7class Base1;
8   extern task nodef();
9   extern task nodef();  // duplicate
10endclass
11
12task Base1::noproto();  // no such prototype
13endtask
14
15module t (/*AUTOARG*/);
16endmodule
17