1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7class Cls; 8 typedef enum {A = 10, B = 20, C = 30} en_t; 9 10 int m_pub = 1; 11 local int m_loc = 2; 12 protected int m_prot = B; 13 task f_pub; endtask 14 local task f_loc; endtask 15 protected task f_prot; endtask 16 static task s_pub; endtask 17 static local task s_loc; endtask 18 static protected task s_prot; endtask 19 task check; 20 Cls o; 21 if (m_pub != 1) $stop; 22 if (m_loc != 2) $stop; 23 if (m_prot != 20) $stop; 24 f_pub(); // Ok 25 f_loc(); // Ok 26 f_prot(); // Ok 27 s_pub(); // Ok 28 s_loc(); // Ok 29 s_prot(); // Ok 30 Cls::s_pub(); // Ok 31 Cls::s_loc(); // Ok 32 Cls::s_prot(); // Ok 33 endtask 34endclass 35 36class Ext extends Cls; 37 task check; 38 if (m_pub != 1) $stop; 39 if (m_prot != 20) $stop; 40 f_pub(); // Ok 41 f_prot(); // Ok 42 s_pub(); // Ok 43 s_prot(); // Ok 44 Cls::s_pub(); // Ok 45 Cls::s_prot(); // Ok 46 endtask 47endclass 48 49module t (/*AUTOARG*/); 50 const Cls mod_c = new; 51 52 initial begin 53 Cls c; 54 Ext e; 55 if (c.A != 10) $stop; 56 c = new; 57 e = new; 58 if (c.m_pub != 1) $stop; 59 // 60 if (mod_c.A != 10) $stop; 61 // 62 c.check(); 63 e.check(); 64 // 65 Cls::s_pub(); // Ok 66 c.s_pub(); // Ok 67 e.s_pub(); // Ok 68 // 69 $write("*-* All Finished *-*\n"); 70 $finish; 71 end 72endmodule 73