1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7class Cls;
8   int imembera;
9endclass : Cls
10
11module t (/*AUTOARG*/);
12   Cls c;
13   initial begin
14      c = null;  // Not really required as null is default
15      c.imembera = 10;  // BAD IEEE 8.4
16      $write("*-* All Finished *-*\n");
17      $finish;
18   end
19endmodule
20