1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7class Cls #(parameter PARAMB = 12);
8endclass
9
10module t (/*AUTOARG*/);
11
12   Cls #(.PARAMBAD(1)) c;  // Bad param name
13   Cls #(13, 1) cd;  // Bad param number
14
15endmodule
16