1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2019 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7virtual class VBase;
8   virtual function int hello;
9      return 1;
10   endfunction
11endclass
12
13class VA extends VBase;
14   virtual function int hello;
15      return 2;
16   endfunction
17endclass
18
19class VB extends VBase;
20   virtual function int hello;
21      return 3;
22   endfunction
23endclass
24
25module t;
26   initial begin
27      VA va = new;
28      VB vb = new;
29      VBase b;
30
31      if (va.hello() != 2) $stop;
32      if (vb.hello() != 3) $stop;
33
34      b = va;
35      if (b.hello() != 2) $stop;
36      b = vb;
37      if (b.hello() != 3) $stop;
38      $write("*-* All Finished *-*\n");
39      $finish;
40   end
41endmodule
42