1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty.
5// SPDX-License-Identifier: CC0-1.0
6
7/* verilator lint_off LITENDIAN */
8module some_module (
9		    input wrclk
10		    );
11
12   logic [ 1 : 0 ] 	  some_state;
13   logic [1:0] 		  some_other_state;
14
15   always @(posedge wrclk) begin
16      case (some_state)
17        2'b11:
18          if (some_other_state == 0)
19            some_state <= 2'b00;
20        default:
21          $display ("This is a display statement");
22      endcase
23
24      if (wrclk)
25        some_other_state <= 0;
26   end
27
28endmodule
29
30`define BROKEN
31
32module t1(
33	  input [-12:-9] i_clks,
34	  input 	 i_clk0,
35	  input 	 i_clk1
36	  );
37
38   some_module
39     some_module
40       (
41`ifdef BROKEN
42	.wrclk (i_clks[-12])
43`else
44	.wrclk (i_clk1)
45`endif
46	);
47endmodule
48
49module t2(
50	  input [2:0] i_clks,
51	  input       i_clk0,
52	  input       i_clk1,
53	  input       i_clk2,
54	  input       i_data
55	  );
56   logic [-12:-9]     the_clks;
57   logic 	      data_q;
58
59   assign the_clks[-12] = i_clk1;
60   assign the_clks[-11] = i_clk2;
61   assign the_clks[-10] = i_clk1;
62   assign the_clks[-9] = i_clk0;
63
64   always @(posedge i_clk0) begin
65      data_q <= i_data;
66   end
67
68   t1 t1
69     (
70      .i_clks (the_clks),
71      .i_clk0 (i_clk0),
72      .i_clk1 (i_clk1)
73      );
74endmodule
75
76module t(
77	 input clk0 /*verilator clocker*/,
78	 input clk1 /*verilator clocker*/,
79	 input clk2 /*verilator clocker*/,
80	 input data_in
81	 );
82
83   logic [2:0] clks;
84
85   assign clks = {1'b0, clk1, clk0};
86
87   t2
88     t2
89       (
90	.i_clks (clks),
91	.i_clk0 (clk0),
92	.i_clk1 (clk1),
93	.i_clk2 (clk2),
94	.i_data (data_in)
95	);
96
97   initial begin
98      $write("*-* All Finished *-*\n");
99      $finish;
100   end
101endmodule
102