1// DESCRIPTION: Verilator: Verilog Test module
2//
3// Copyright 2021 by Geza Lore. This program is free software; you can
4// redistribute it and/or modify it under the terms of either the GNU
5// Lesser General Public License Version 3 or the Perl Artistic License
6// Version 2.0.
7// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
8
9// From issue #3096
10
11module decoder(
12               input wire [31:0] instr_i,
13               // Making 'a' an output preserves it as a sub-expression and causes a missing clean
14               output wire       a,
15               output wire       illegal_instr_o
16               );
17   /* verilator lint_off WIDTH */
18   wire                          b = ! instr_i[12:5];
19   wire                          c = ! instr_i[1:0];
20   wire                          d = ! instr_i[15:13];
21   /* verilator lint_on WIDTH */
22   assign a = d ? b : 1'h1;
23   assign illegal_instr_o = c ? a : 1'h0;
24endmodule
25