1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t(/*AUTOARG*/);
8
9   function int f;
10      #1 $stop;
11      f = 0;
12   endfunction
13
14   int i;
15
16   initial begin
17      i = f();
18      $write("*-* All Finished *-*\n");
19      $finish;
20   end
21
22   final begin
23      #1;
24      $stop;
25   end
26
27endmodule
28