1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2003 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t;
8   reg signed [20:0] longp;
9   reg signed [20:0] longn;
10   reg signed [40:0] quadp;
11   reg signed [40:0] quadn;
12   reg signed [80:0] widep;
13   reg signed [80:0] widen;
14
15   initial begin
16      longp = 21'shbbccc;
17      longn = 21'shbbccc; longn[20] = 1'b1;
18      quadp = 41'sh1_bbbb_cccc;
19      quadn = 41'sh1_bbbb_cccc; quadn[40] = 1'b1;
20      widep = 81'shbc_1234_5678_1234_5678;
21      widen = 81'shbc_1234_5678_1234_5678; widen[40] = 1'b1;
22
23      // Display formatting
24      $display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p",
25               $time, longp, longp, longp, longp, longp, longp, longp, longp);
26      $display("[%0t] ln %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p",
27               $time, longn, longn, longn, longn, longn, longn, longn, longn);
28      $display("[%0t] qp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p",
29               $time, quadp, quadp, quadp, quadp, quadp, quadp, quadp, quadp);
30      $display("[%0t] qn %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p",
31               $time, quadn, quadn, quadn, quadn, quadn, quadn, quadn, quadn);
32      $display("[%0t] wp %%x=%x %%x=%x %%o=%o %%b=%b %%p=%p %%0p=%0p",
33               $time, widep, widep, widep, widep, widep, widep);
34      $display("[%0t] wn %%x=%x %%x=%x %%o=%o %%b=%b %%p=%p %%0p=%0p",
35               $time, widen, widen, widen, widen, widen, widen);
36      $display;
37      $write("*-* All Finished *-*\n");
38      $finish;
39   end
40endmodule
41