1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2010 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7typedef enum { EN_ZERO,
8	       EN_ONE
9	       } En_t;
10
11module t (/*AUTOARG*/
12   // Inputs
13   clk
14   );
15   input clk;
16
17   // Insure that we can declare a type with a function declaration
18   function enum integer {
19			  EF_TRUE = 1,
20			  EF_FALSE = 0 }
21				    f_enum_inv ( input a);
22      f_enum_inv = a ? EF_FALSE : EF_TRUE;
23   endfunction
24   initial begin
25      if (f_enum_inv(1) != 0) $stop;
26      if (f_enum_inv(0) != 1) $stop;
27   end
28
29   En_t a, z;
30
31   sub sub (/*AUTOINST*/
32	    // Outputs
33	    .z				(z),
34	    // Inputs
35	    .a				(a));
36
37   integer    cyc; initial cyc=1;
38   always @ (posedge clk) begin
39      if (cyc!=0) begin
40	 cyc <= cyc + 1;
41	 if (cyc==1) begin
42	    a <= EN_ZERO;
43	 end
44	 if (cyc==2) begin
45	    a <= EN_ONE;
46	    if (z != EN_ONE) $stop;
47	 end
48	 if (cyc==3) begin
49	    if (z != EN_ZERO) $stop;
50	 end
51	 if (cyc==9) begin
52	    $write("*-* All Finished *-*\n");
53	    $finish;
54	 end
55      end
56   end
57
58endmodule
59
60module sub (input En_t a, output En_t z);
61   always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE;
62endmodule
63
64// Local Variables:
65// verilog-typedef-regexp: "_t$"
66// End:
67