1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2014 by Jonathon Donaldson. 5// SPDX-License-Identifier: CC0-1.0 6 7// bug855 8module our; 9 10 typedef enum logic {n,N} T_Flg_N; 11 12 typedef struct packed { 13 T_Flg_N N; 14 } T_PS_Reg; 15 16 T_PS_Reg PS = 1'b1; 17 18 initial begin 19 $write ("P:%s\n", PS.N.name); 20 $write("*-* All Finished *-*\n"); 21 $finish; 22 end 23 24endmodule 25