1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2014 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); 8`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); 9 10module t (/*AUTOARG*/ 11 // Inputs 12 clk 13 ); 14 input clk; 15 16 typedef enum [3:0] { 17 E01 = 1, 18 E03 = 3, 19 E04 = 4 20 } my_t; 21 22 integer cyc = 0; 23 my_t e; 24 25 int arrayfits [e.num]; // Check can use as constant 26 27 string all; 28 29 // Check constification 30 initial begin 31 e = E03; 32 `checkh(e.first, E01); 33 `checkh(e.last, E04); 34 `checkh(e.last(), E04); 35 `checkh(e.next, E04); 36 `checkh(e.next(), E04); 37 `checkh(e.next(1), E04); 38 `checkh(e.next(1).next(1), E01); 39 `checkh(e.next(2), E01); 40 `checkh(e.next(1).next(1).next(1), E03); 41 `checkh(e.next(1).next(2), E03); 42 `checkh(e.next(3), E03); 43 `checkh(e.prev, E01); 44 `checkh(e.prev(1), E01); 45 `checkh(e.prev(1).prev(1), E04); 46 `checkh(e.prev(2), E04); 47 `checkh(e.num, 3); 48 `checks(e.name, "E03"); 49 // 50 all = ""; 51 for (my_t e = e.first; e != e.last; e = e.next) begin 52 all = {all, e.name}; 53 end 54 e = e.last; 55 all = {all, e.name}; 56 `checks(all, "E01E03E04"); 57 end 58 59 // Check runtime 60 always @ (posedge clk) begin 61 cyc <= cyc + 1; 62 if (cyc==0) begin 63 // Setup 64 e <= E01; 65 end 66 else if (cyc==1) begin 67 `checks(e.name, "E01"); 68 `checkh(e.next, E03); 69 `checkh(e.next(1), E03); 70 `checkh(e.next(2), E04); 71 `checkh(e.prev, E04); 72 `checkh(e.prev(1), E04); 73 `checkh(e.prev(2), E03); 74 e <= E03; 75 end 76 else if (cyc==2) begin 77 `checks(e.name, "E03"); 78 `checkh(e.next, E04); 79 `checkh(e.next(1), E04); 80 `checkh(e.next(2), E01); 81 `checkh(e.prev, E01); 82 `checkh(e.prev(1), E01); 83 `checkh(e.prev(2), E04); 84 e <= E04; 85 end 86 else if (cyc==3) begin 87 `checks(e.name, "E04"); 88 `checkh(e.next, E01); 89 `checkh(e.next(1), E01); 90 `checkh(e.next(2), E03); 91 `checkh(e.prev, E03); 92 `checkh(e.prev(1), E03); 93 `checkh(e.prev(2), E01); 94 e <= E01; 95 end 96 else if (cyc==99) begin 97 $write("*-* All Finished *-*\n"); 98 $finish; 99 end 100 end 101 102endmodule 103