1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t();
8   typedef integer q_t[$];
9
10   function void queue_set(ref q_t q);
11`ifdef TEST_NOINLINE
12      // verilator no_inline_task
13`endif
14      q.push_back(42);
15   endfunction
16
17   function void queue_check_nref(q_t q);
18`ifdef TEST_NOINLINE
19      // verilator no_inline_task
20`endif
21      q[0] = 11;
22      if (q[0] != 11) $stop;
23   endfunction
24
25   function void queue_check_ref(const ref q_t q);
26`ifdef TEST_NOINLINE
27      // verilator no_inline_task
28`endif
29      if (q[0] != 42) $stop;
30   endfunction
31
32   function q_t queue_ret();
33`ifdef TEST_NOINLINE
34      // verilator no_inline_task
35`endif
36      queue_ret = '{101};
37   endfunction
38
39   initial begin
40      q_t iq;
41      queue_set(iq);
42      queue_check_ref(iq);
43
44      iq[0] = 44;
45      queue_check_nref(iq);
46      if (iq[0] != 44) $stop;
47
48      iq = queue_ret();
49      if (iq[0] != 101) $stop;
50
51      $write("*-* All Finished *-*\n");
52      $finish;
53   end
54endmodule
55