1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2006 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   // verilator lint_off MULTIDRIVEN
13
14   ma ma0 ();
15
16   initial t.ma0.u_b[0].f(1);
17   initial t.ma0.u_b[0].f(clk);
18
19   global_mod #(32'hf00d) global_cell ();
20   global_mod #(32'hf22d) global_cell2 ();
21
22   input clk;
23   integer cyc=1;
24
25   function [31:0] getName;  input fake;  getName = "t   "; endfunction
26
27   always @ (posedge clk) begin
28      cyc <= cyc + 1;
29      if (cyc==2) begin
30	 if (global_cell. getGlob(1'b0)  !== 32'hf00d) $stop;
31	 if (global_cell2.getGlob(1'b0) !== 32'hf22d) $stop;
32      end
33      if (cyc==3) begin
34	 if (ma0.        getName(1'b0) !== "ma  ") $stop;
35	 if (ma0.mb0.    getName(1'b0) !== "mb  ") $stop;
36	 if (ma0.mb0.mc0.getName(1'b0) !== "mc  ") $stop;
37      end
38      if (cyc==4) begin
39	 if (ma0.mb0.    getP2(1'b0) !== 32'h0) $stop;
40	 if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop;
41	 if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop;
42      end
43      if (cyc==5) begin
44	 ma0.        checkName(ma0.        getName(1'b0));
45	 ma0.mb0.    checkName(ma0.mb0.    getName(1'b0));
46	 ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0));
47      end
48      if (cyc==9) begin
49	 $write("*-* All Finished *-*\n");
50	 $finish;
51      end
52   end
53
54endmodule
55
56`ifdef ATTRIBUTES
57 `ifdef USE_INLINE_MID
58  `define INLINE_MODULE /*verilator inline_module*/
59  `define INLINE_MID_MODULE /*verilator no_inline_module*/
60 `else
61  `ifdef USE_INLINE
62   `define INLINE_MODULE /*verilator inline_module*/
63   `define INLINE_MID_MODULE /*verilator inline_module*/
64  `else
65   `define INLINE_MODULE /*verilator public_module*/
66   `define INLINE_MID_MODULE /*verilator public_module*/
67  `endif
68 `endif
69`else
70 `define INLINE_MODULE
71 `define INLINE_MID_MODULE
72`endif
73
74module global_mod;
75   `INLINE_MODULE
76   parameter INITVAL = 0;
77   integer globali;
78
79   initial globali = INITVAL;
80   function [31:0] getName;  input fake;  getName = "gmod"; endfunction
81   function [31:0] getGlob;  input fake;  getGlob = globali;  endfunction
82endmodule
83
84module ma ();
85   `INLINE_MODULE
86
87   mb #(0) mb0 ();
88   reg [31:0] gName; initial gName = "ma  ";
89   function [31:0] getName;  input fake;  getName = "ma  "; endfunction
90   task checkName; input [31:0] name;  if (name !== "ma  ") $stop; endtask
91
92   initial begin
93      if (ma.getName(1'b0) !== "ma  ") $stop;
94      if (mb0.getName(1'b0) !== "mb  ") $stop;
95      if (mb0.mc0.getName(1'b0) !== "mc  ") $stop;
96   end
97endmodule
98
99module mb ();
100   `INLINE_MID_MODULE
101   parameter P2 = 0;
102
103   mc #(P2,0) mc0 ();
104   mc #(P2,1) mc1 ();
105   global_mod #(32'hf33d) global_cell2 ();
106
107   reg [31:0] gName; initial gName = "mb  ";
108   function [31:0] getName;  input fake;  getName = "mb  "; endfunction
109   function [31:0] getP2  ;  input fake;  getP2 = P2;       endfunction
110   task checkName; input [31:0] name;  if (name !== "mb  ") $stop; endtask
111
112   initial begin
113`ifndef verilator #1; `endif
114      if (ma. getName(1'b0) !== "ma  ") $stop;
115      if (    getName(1'b0) !== "mb  ") $stop;
116      if (mc1.getName(1'b0) !== "mc  ") $stop;
117
118      ma. checkName (ma. gName);
119      /**/checkName (    gName);
120      mc1.checkName (mc1.gName);
121      ma. checkName (ma. getName(1'b0));
122      /**/checkName (    getName(1'b0));
123      mc1.checkName (mc1.getName(1'b0));
124   end
125endmodule
126
127module mc ();
128   `INLINE_MODULE
129    parameter P2 = 0;
130    parameter P3 = 0;
131
132   reg [31:0] gName; initial gName = "mc  ";
133   function [31:0] getName;  input fake;  getName = "mc  "; endfunction
134   function [31:0] getP3  ;  input fake;  getP3 = P3;       endfunction
135   task checkName; input [31:0] name;  if (name !== "mc  ") $stop; endtask
136
137   initial begin
138`ifndef verilator #1; `endif
139      if (ma.getName(1'b0) !== "ma  ") $stop;
140      if (mb.getName(1'b0) !== "mb  ") $stop;
141      if (mc.getName(1'b0) !== "mc  ") $stop;
142      ma.checkName (ma.gName);
143      mb.checkName (mb.gName);
144      mc.checkName (mc.gName);
145      ma.checkName (ma.getName(1'b0));
146      mb.checkName (mb.getName(1'b0));
147      mc.checkName (mc.getName(1'b0));
148   end
149endmodule
150
151module b;
152
153   function void f(bit v);
154      $display("%m");
155   endfunction : f;
156
157endmodule : b
158
159bind ma b u_b[0:1];
160