1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2003 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (clk); 8 input clk; 9 10 // verilator lint_off WIDTH 11 12`define INT_RANGE 31:0 13`define INT_RANGE_MAX 31 14`define VECTOR_RANGE 63:0 15 16 reg [`INT_RANGE] stashb, stasha, stashn, stashm; 17 18 function [`VECTOR_RANGE] copy_range; 19 input [`VECTOR_RANGE] y; 20 input [`INT_RANGE] b; 21 input [`INT_RANGE] a; 22 23 input [`VECTOR_RANGE] x; 24 input [`INT_RANGE] n; 25 input [`INT_RANGE] m; 26 27 begin 28 copy_range = y; 29 stashb = b; 30 stasha = a; 31 stashn = n; 32 stashm = m; 33 end 34 endfunction 35 36 parameter DATA_SIZE = 16; 37 parameter NUM_OF_REGS = 32; 38 39 reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf; 40 reg [DATA_SIZE-1:0] memread_rf_reg; 41 always @(memread_rf) begin : memread_convert 42 memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf, 43 DATA_SIZE-'d1, DATA_SIZE-'d1); 44 end 45 46 integer cyc; initial cyc=1; 47 always @ (posedge clk) begin 48 if (cyc!=0) begin 49 cyc <= cyc + 1; 50 if (cyc==1) begin 51 memread_rf = 512'haa; 52 end 53 if (cyc==3) begin 54 if (stashb != 'd15) $stop; 55 if (stasha != 'd15) $stop; 56 if (stashn != 'd15) $stop; 57 if (stashm != 'd15) $stop; 58 $write("*-* All Finished *-*\n"); 59 $finish; 60 end 61 end 62 end 63 64endmodule 65