1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2011 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7// bug420
8typedef logic [7-1:0] wb_ind_t;
9typedef logic [7-1:0] id_t;
10
11module t (/*AUTOARG*/
12   // Inputs
13   clk
14   );
15   input clk;
16
17   integer 	cyc = 0;
18   reg [63:0] 	crc;
19   reg [63:0] 	sum;
20
21   // Take CRC data and apply to testblock inputs
22   wire [31:0]  in = crc[31:0];
23
24   /*AUTOWIRE*/
25
26   wire [6:0] out = line_wb_ind( in[6:0] );
27
28   // Aggregate outputs into a single result vector
29   wire [63:0] result = {57'h0, out};
30
31   // Test loop
32   always @ (posedge clk) begin
33`ifdef TEST_VERBOSE
34      $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
35`endif
36      cyc <= cyc + 1;
37      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
38      sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
39      if (cyc==0) begin
40	 // Setup
41	 crc <= 64'h5aef0c8d_d70a4497;
42	 sum <= 64'h0;
43      end
44      else if (cyc<10) begin
45	 sum <= 64'h0;
46      end
47      else if (cyc<90) begin
48      end
49      else if (cyc==99) begin
50	 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
51	 if (crc !== 64'hc77bb9b3784ea091) $stop;
52	 // What checksum will we end up with (above print should match)
53`define EXPECTED_SUM 64'hc918fa0aa882a206
54	 if (sum !== `EXPECTED_SUM) $stop;
55	 $write("*-* All Finished *-*\n");
56	 $finish;
57      end
58   end
59
60   function wb_ind_t line_wb_ind( id_t id );
61      if( id[$bits(id_t)-1] == 0 )
62        return {2'b00, id[$bits(wb_ind_t)-3:0]};
63      else
64        return {2'b01, id[$bits(wb_ind_t)-3:0]};
65   endfunction // line_wb_ind
66
67endmodule
68