1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2021 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7function int zeroed;
8endfunction
9
10function automatic integer what_bit;
11   input [31:0] a;
12   // what_bit = 0;
13   for (int i = 31; i >= 0; i = i - 1) begin
14      if (a[i] == 1'b1) begin
15         what_bit = i;
16      end
17   end
18endfunction
19
20module t(/*AUTOARG*/);
21
22   parameter ZERO = zeroed();
23
24   parameter PP = what_bit(0);
25
26   initial begin
27      if (ZERO != 0) $stop;
28      if (PP != 'x) $stop;
29      $write("*-* All Finished *-*\n");
30      $finish;
31   end
32
33endmodule
34