1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2005 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 integer cyc; initial cyc=1; 14 15 reg b; 16 17 wire vconst1 = 1'b0; 18 wire vconst2 = !(vconst1); 19 wire vconst3 = !vconst2; 20 wire vconst = vconst3; 21 22 wire qa; 23 wire qb; 24 wire qc; 25 wire qd; 26 wire qe; 27 ta ta (.b(b), .vconst(vconst), .q(qa)); 28 tb tb (.clk(clk), .vconst(vconst), .q(qb)); 29 tc tc (.b(b), .vconst(vconst), .q(qc)); 30 td td (.b(b), .vconst(vconst), .q(qd)); 31 te te (.clk(clk), .b(b), .vconst(vconst), .q(qe)); 32 33 always @ (posedge clk) begin 34`ifdef TEST_VERBOSE 35 $display("%b",{qa,qb,qc,qd,qe}); 36`endif 37 if (cyc!=0) begin 38 cyc <= cyc + 1; 39 if (cyc==1) begin 40 b <= 1'b1; 41 end 42 if (cyc==2) begin 43 if (qa!=1'b1) $stop; 44 if (qb!=1'b0) $stop; 45 if (qd!=1'b0) $stop; 46 b <= 1'b0; 47 end 48 if (cyc==3) begin 49 if (qa!=1'b0) $stop; 50 if (qb!=1'b0) $stop; 51 if (qd!=1'b0) $stop; 52 if (qe!=1'b0) $stop; 53 b <= 1'b1; 54 end 55 if (cyc==4) begin 56 if (qa!=1'b1) $stop; 57 if (qb!=1'b0) $stop; 58 if (qd!=1'b0) $stop; 59 if (qe!=1'b1) $stop; 60 b <= 1'b0; 61 end 62 if (cyc==5) begin 63 $write("*-* All Finished *-*\n"); 64 $finish; 65 end 66 end 67 end 68endmodule 69 70module ta ( 71 input vconst, 72 input b, 73 output reg q); 74 75 always @ (/*AS*/b or vconst) begin 76 q = vconst | b; 77 end 78endmodule 79 80module tb ( 81 input vconst, 82 input clk, 83 output reg q); 84 85 always @ (posedge clk) begin 86 q <= vconst; 87 end 88endmodule 89 90module tc ( 91 input vconst, 92 input b, 93 output reg q); 94 always @ (posedge vconst) begin 95 q <= b; 96 $stop; 97 end 98endmodule 99 100module td ( 101 input vconst, 102 input b, 103 output reg q); 104 105 always @ (/*AS*/vconst) begin 106 q = vconst; 107 end 108endmodule 109 110module te ( 111 input clk, 112 input vconst, 113 input b, 114 output reg q); 115 reg qmid; 116 always @ (posedge vconst or posedge clk) begin 117 qmid <= b; 118 end 119 always @ (posedge clk or posedge vconst) begin 120 q <= qmid; 121 end 122endmodule 123