1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2012 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/); 8 a a (); 9 defparam a.b.W = 3; 10endmodule 11 12module a; 13 b b(); 14endmodule 15 16module b; 17 parameter W = 0; 18endmodule 19