1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2020 by Yutetsu TAKATSUKASA 5 6module t; 7 t_flag_relinc_sub i_t_flag_relinc_sub(); 8endmodule 9 10`ifdef VERILATOR 11`verilator_config 12hier_block -module "t_flag_relinc_sub" 13`verilog 14`endif 15