1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty, 2012 by Iztok Jeras.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   input clk;
13
14   parameter SIZE = 8;
15
16   integer cnt = 0;
17
18   logic [SIZE-1:0] vld_for;
19   logic            vld_if   = 1'b0;
20   logic            vld_else = 1'b0;
21
22   genvar i;
23
24   // event counter
25   always @ (posedge clk) begin
26      cnt <= cnt + 1;
27   end
28
29   // finish report
30   always @ (posedge clk)
31   if (cnt==SIZE) begin : if_cnt_finish
32      $write("*-* All Finished *-*\n");
33      $finish;
34   end : if_cnt_finish_bad
35
36   generate
37   for (i=0; i<SIZE; i=i+1) begin : generate_for
38      always @ (posedge clk)
39      if (cnt == i)  vld_for[i] <= 1'b1;
40   end : generate_for_bad
41   endgenerate
42
43   generate
44   if (SIZE>0) begin : generate_if_if
45      always @ (posedge clk)
46      vld_if <= 1'b1;
47   end : generate_if_if_bad
48   else begin : generate_if_else
49      always @ (posedge clk)
50      vld_else <= 1'b1;
51   end : generate_if_else_bad
52   endgenerate
53
54endmodule : t_bad
55