1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2005 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   input clk;
13   integer cyc; initial cyc = 0;
14
15   reg [7:0] crc;
16   reg [2:0] sum;
17   wire [2:0] in = crc[2:0];
18   wire [2:0] out;
19
20   MxN_pipeline pipe (in, out, clk);
21
22   always @ (posedge clk) begin
23      //$write("[%0t] cyc==%0d crc=%b sum=%x\n", $time, cyc, crc, sum);
24      cyc <= cyc + 1;
25      crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
26      if (cyc==0) begin
27	 // Setup
28	 crc <= 8'hed;
29	 sum <= 3'h0;
30      end
31      else if (cyc>10 && cyc<90) begin
32	 sum <= {sum[1:0],sum[2]} ^ out;
33      end
34      else if (cyc==99) begin
35	 if (crc !== 8'b01110000) $stop;
36	 if (sum !== 3'h3) $stop;
37	 $write("*-* All Finished *-*\n");
38	 $finish;
39      end
40   end
41endmodule
42
43module dffn (q,d,clk);
44   parameter BITS = 1;
45
46   input [BITS-1:0]  d;
47   output reg [BITS-1:0] q;
48   input 	     clk;
49
50   always @ (posedge clk) begin
51      q <= d;
52   end
53
54endmodule
55
56module MxN_pipeline (in, out, clk);
57   parameter M=3, N=4;
58
59   input [M-1:0] in;
60   output [M-1:0] out;
61   input 	  clk;
62
63   // Unsupported: Per-bit array instantiations with output connections to non-wires.
64   //wire [M*(N-1):1] t;
65   //dffn #(M) p[N:1] ({out,t},{t,in},clk);
66
67   wire [M*(N-1):1] w;
68   wire [M*N:1] q;
69   dffn #(M) p[N:1] (q,{w,in},clk);
70   assign 	{out,w} = q;
71
72endmodule
73