1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2004 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   input clk;
13   integer cyc; initial cyc=1;
14
15   reg [41:0] 		aaa;
16   wire [41:0] 		bbb;
17
18   // verilator public_module
19   wire [41:0] 		z_0;
20   wire [41:0] 		z_1;
21
22   wide w_0(
23	    .xxx( { {40{1'b0}},2'b11 } ),
24	    .yyy( aaa[1:0] ),
25	    .zzz( z_0 )
26	    );
27
28   wide w_1(
29	    .xxx( aaa ),
30	    .yyy( 2'b10 ),
31	    .zzz( z_1 )
32	    );
33
34   assign bbb= z_0 + z_1;
35
36   always @ (posedge clk) begin
37      if (cyc!=0) begin
38	 cyc <= cyc + 1;
39	 if (cyc==1) begin
40	    aaa <= 42'b01;
41	 end
42	 if (cyc==2) begin
43	    aaa <= 42'b10;
44	    if (z_0 != 42'h4) $stop;
45	    if (z_1 != 42'h3) $stop;
46	 end
47	 if (cyc==3) begin
48	    if (z_0 != 42'h5) $stop;
49	    if (z_1 != 42'h4) $stop;
50	 end
51	 if (cyc==4) begin
52	    $write("*-* All Finished *-*\n");
53	    $finish;
54	 end
55      end
56   end
57
58endmodule
59
60module wide (
61	input [41:0]		xxx,
62	input [1:0]			yyy,
63	output [41:0]		zzz
64	);
65   // verilator public_module
66
67   assign zzz = xxx+ { {40{1'b0}},yyy };
68
69endmodule
70