1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty.
5// SPDX-License-Identifier: CC0-1.0
6
7// bug1001
8
9interface intf
10  #(parameter PARAM = 0)
11   ();
12   logic val;
13endinterface
14
15module t();
16
17   generate
18      if (1) begin
19         intf #(.PARAM(2)) my_intf ();
20         assign my_intf.val = '1;
21      end else begin
22         intf #(.PARAM(3)) my_intf ();
23         assign my_intf.val = '0;
24      end
25   endgenerate
26
27   generate
28      begin
29	 if (1) begin
30            intf #(.PARAM(2)) my_intf ();
31            assign my_intf.val = '1;
32	 end else begin
33            intf #(.PARAM(3)) my_intf ();
34            assign my_intf.val = '0;
35	 end
36      end
37   endgenerate
38
39   generate
40      begin
41	 begin
42	    if (1) begin
43               intf #(.PARAM(2)) my_intf ();
44               assign my_intf.val = '1;
45	    end else begin
46               intf #(.PARAM(3)) my_intf ();
47               assign my_intf.val = '0;
48	    end
49	 end
50      end
51   endgenerate
52
53   initial begin
54      $write("*-* All Finished *-*\n");
55      $finish;
56   end
57endmodule
58